A CMOS 18 THzΩ 248 Mb/s transimpedance amplifier and 155 Mb/s LED-driver for low cost optical fiber links. - Mark Ingels; Geert Van der Plas; Jan Crols; Michiel Steyaert (IEEE J. Solid State Circuits, 1994)

An analogue module generator for mixed analogue/digital asic design. - Georges G. E. Gielen; Geert Debyser; Koen Lampaert; Francky Leyn; Koen Swings; Geert Van der Plas; Willy Sansen; Domine Leenaerts; Petar Veselinovic; W. van Bokhoven (Int. J. Circuit Theory Appl., 1995)

ADMIRE: advanced mixed signal design environment. - Philippe Reynaert; Ludwig G. A. Callewaert; Georges G. E. Gielen; Geert Debyser; Koen Lampaert; Francky Leyn; Geert Van der Plas; Willy Sansen; Birger Schneider; René Bloch; Dave Orton; Steve Boardman; et al. (ICECS, 1996)

Automated test pattern generation for analog integrated circuits. - Wim Verhaegen; Geert Van der Plas; Georges G. E. Gielen (VTS, 1997)

A 12 bit 200 MHz low glitch CMOS D/A converter. - Anne Van den Bosch; Marc Borremans; Jan Vandenbussche; Geert Van der Plas; Augusto Manuel Marques; José Bastos; Michiel Steyaert; Georges G. E. Gielen; Willy Sansen (CICC, 1998)

Mondriaan: a tool for automated layout synthesis of array-type analog blocks. - Geert Van der Plas; Jan Vandenbussche; Georges G. E. Gielen; Willy Sansen (CICC, 1998)

Behavioral model for D/A converters as VSI virtual components. - Jan Vandenbussche; Geert Van der Plas; Georges G. E. Gielen; Michiel Steyaert; Willy Sansen (CICC, 1998)

Statistical behavioral modeling for A/D-converters. - Geert Van der Plas; Jan Vandenbussche; Wim Verhaegen; Georges G. E. Gielen; Willy Sansen (ICECS, 1999)

A 14-bit intrinsic accuracy Q2 random walk CMOS DAC. - Geert Van der Plas; Jan Vandenbussche; Willy Sansen; Michel S. J. Steyaert; Georges G. E. Gielen (IEEE J. Solid State Circuits, 1999)

Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter. - Geert Van der Plas; Jan Vandenbussche; Walter Daems; Antal van den Bosch; Georges G. E. Gielen; Willy M. C. Sansen (DAC, 2000)

CYCLONE: automated design and layout of RF LC-oscillators. - Carl De Ranter; Bram De Muer; Geert Van der Plas; Peter J. Vancorenland; Michiel Steyaert; Georges G. E. Gielen; Willy M. C. Sansen (DAC, 2000)

A Layout-Aware Synthesis Methodology for RF Circuits. - Peter J. Vancorenland; Geert Van der Plas; Michiel Steyaert; Georges G. E. Gielen; Willy M. C. Sansen (ICCAD, 2001)

AMGIE-A synthesis environment for CMOS analog integrated circuits. - Geert Van der Plas; Geert Debyser; Francky Leyn; Koen Lampaert; Jan Vandenbussche; Georges G. E. Gielen; Willy M. C. Sansen; Petar Veselinovic; Domine Leenaerts (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

A layout synthesis methodology for array-type analog blocks. - Geert Van der Plas; Jan Vandenbussche; Georges G. E. Gielen; Willy M. C. Sansen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

CYCLONE: automated design and layout of RF LC-oscillators. - Carl De Ranter; Geert Van der Plas; Michiel Steyaert; Georges G. E. Gielen; Willy M. C. Sansen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. - Mustafa Badaroglu; Lakshmanan Balasubramanian; Kris Tiri; Vincent Gravot; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (ESSCIRC, 2003)

Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]. - Mustafa Badaroglu; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (CICC, 2004)

High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. - Geert Van der Plas; Mustafa Badaroglu; Gerd Vandersteen; Petr Dobrovolný; Piet Wambacq; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (DAC, 2004)

Digital Ground Bounce Reduction by Phase Modulation of the Clock. - Mustafa Badaroglu; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (DATE, 2004)

A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL. - Tao Chen; Peter Geens; Geert Van der Plas; Wim Dehaene; Georges G. E. Gielen (ESSCIRC, 2004)

Performance degradation of an LC-tank VCO by impact of digital switching noise. - Charlotte Soens; Geert Van der Plas; Piet Wambacq; Stéphane Donnay (ESSCIRC, 2004)

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. - Mustafa Badaroglu; Geert Van der Plas; Piet Wambacq; Lakshmanan Balasubramanian; Kris Tiri; Ingrid Verbauwhede; Stéphane Donnay; Georges G. E. Gielen; Hugo J. De Man (IEEE J. Solid State Circuits, 2004)

A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC. - Jurgen Deveugele; Geert Van der Plas; Michiel Steyaert; Georges G. E. Gielen; Willy M. C. Sansen (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Substrate noise immune design of an LC-tank VCO using sensitivity functions. - Charlotte Soens; Geert Van der Plas; Piet Wambacq; Stéphane Donnay (CICC, 2005)

Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. - Charlotte Soens; Geert Van der Plas; Piet Wambacq; Stéphane Donnay (DATE, 2005)

Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates. - Charlotte Soens; Geert Van der Plas; Piet Wambacq; Stéphane Donnay; Maarten Kuijk (IEEE J. Solid State Circuits, 2005)

Digital ground bounce reduction by supply current shaping and clock frequency Modulation. - Mustafa Badaroglu; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation. - Julien Ryckaert; Claude Desset; Andrew Fort; Mustafa Badaroglu; Vincent De Heyn; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Bart van Poucke; Bert Gyselinckx (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW. - Pierluigi Nuzzo 001; Geert Van der Plas; Fernando De Bernardinis; Liesbet Van der Perre; Bert Gyselinckx; Pierangelo Terreni (DAC, 2006)

A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process. - Geert Van der Plas; Stefaan Decoutere; Stéphane Donnay (ISSCC, 2006)

A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS. - Julien Ryckaert; Mustafa Badaroglu; Vincent De Heyn; Geert Van der Plas; Pierluigi Nuzzo 001; Andrea Baschirotto; Stefano D'Amico; Claude Desset; Hans Suys; Michael Libois; Bart van Poucke; Piet Wambacq; et al. (ISSCC, 2006)

Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling. - Mustafa Badaroglu; Claude Desset; Julien Ryckaert; Vincent De Heyn; Geert Van der Plas; Piet Wambacq; Bart van Poucke (EURASIP J. Wirel. Commun. Netw., 2006)

Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate. - Charlotte Soens; Geert Van der Plas; Mustafa Badaroglu; Piet Wambacq; Stéphane Donnay; Yves Rolain; Maarten Kuijk (IEEE J. Solid State Circuits, 2006)

Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. - Mustafa Badaroglu; Kris Tiri; Geert Van der Plas; Piet Wambacq; Ingrid Verbauwhede; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Evolution of substrate noise generation mechanisms with CMOS technology scaling. - Mustafa Badaroglu; Piet Wambacq; Geert Van der Plas; Stéphane Donnay; Georges G. E. Gielen; Hugo J. De Man (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

SWAN: high-level simulation methodology for digital substrate noise generation. - Mustafa Badaroglu; Geert Van der Plas; Piet Wambacq; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's. - Stephane Bronckers; Charlotte Soens; Geert Van der Plas; Gerd Vandersteen; Yves Rolain (DATE, 2007)

A switchable low-area 2.4-and-5 GHz dual-band LNA in digital CMOS. - Jonathan Borremans; Piet Wambacq; Geert Van der Plas; Yves Rolain; Maarten Kuijk (ESSCIRC, 2007)

A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS. - Vincent De Heyn; Geert Van der Plas; Julien Ryckaert; Jan Craninckx (ESSCIRC, 2007)

Scalable Gate-Level Models for Power and Timing Analysis. - Mustafa Badaroglu; Geert Van der Plas; Piet Wambacq; Stéphane Donnay; Georges G. E. Gielen; Hugo De Man (ISCAS, 2007)

A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS. - Jan Craninckx; Geert Van der Plas (ISSCC, 2007)

A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a. - Julien Ryckaert; Geert Van der Plas; Vincent De Heyn; Claude Desset; Geert Vanwijnsberghe; Bart van Poucke; Jan Craninckx (ISSCC, 2007)

A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a. - Julien Ryckaert; Geert Van der Plas; Vincent De Heyn; Claude Desset; Bart van Poucke; Jan Craninckx (IEEE J. Solid State Circuits, 2007)

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication. - Julien Ryckaert; Marian Verhelst; Mustafa Badaroglu; Stefano D'Amico; Vincent De Heyn; Claude Desset; Pierluigi Nuzzo 001; Bart van Poucke; Piet Wambacq; Andrea Baschirotto; Wim Dehaene; Geert Van der Plas (IEEE J. Solid State Circuits, 2007)

The Potential of FinFETs for Analog and RF Circuit Applications. - Piet Wambacq; Bob Verbruggen; Karen Scheir; Jonathan Borremans; Morin Dehan; Dimitri Linten; Vincent De Heyn; Geert Van der Plas; Abdelkarim Mercha; Bertrand Parvais; Cedric Gustin; Vaidyanathan Subramanian; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications. - Pierluigi Nuzzo; Claudio Nani; Sergio Saponara; Luca Fanucci; Geert Van der Plas (DATE, 2008)

An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS. - Vito Giannini; Pierluigi Nuzzo 001; Vincenzo Chironi; Andrea Baschirotto; Geert Van der Plas; Jan Craninckx (ISSCC, 2008)

A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC. - Geert Van der Plas; Bob Verbruggen (ISSCC, 2008)

A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS. - Bob Verbruggen; Jan Craninckx; Maarten Kuijk; Piet Wambacq; Geert Van der Plas (ISSCC, 2008)

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies. - Piet Wambacq; Abdelkarim Mercha; Karen Scheir; Bob Verbruggen; Jonathan Borremans; Vincent De Heyn; Steven Thijs; Dimitri Linten; Geert Van der Plas; Bertrand Parvais; Morin Dehan; Stefaan Decoutere; et al. (ISSCC, 2008)

A 150 MS/s 133 µW 7 bit ADC in 90 nm Digital CMOS. - Geert Van der Plas; Bob Verbruggen (IEEE J. Solid State Circuits, 2008)

Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures. - Pierluigi Nuzzo 001; Fernando De Bernardinis; Pierangelo Terreni; Geert Van der Plas (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Evaluation of energy-recovering interconnects for low-power 3D stacked ICs. - Panagiotis Asimakopoulos; Geert Van der Plas; Alexandre Yakovlev; Paul Marchal (3DIC, 2009)

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study. - Dragomir Milojevic; Trevor E. Carlson; Kris Croes; Riko Radojcic; Diana F. Ragett; Dirk Seynhaeve; Federico Angiolini; Geert Van der Plas; Paul Marchal (3DIC, 2009)

A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS. - Pieter Crombez; Geert Van der Plas; Michiel Steyaert; Jan Craninckx (ESSCIRC, 2009)

A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS. - Lynn Bos; Gerd Vandersteen; Julien Ryckaert; Pieter Rombouts; Yves Rolain; Geert Van der Plas (ISSCC, 2009)

Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters. - Sergio Saponara; Pierluigi Nuzzo; Claudio Nani; Geert Van der Plas; Luca Fanucci (IEICE Trans. Electron., 2009)

A Low-Power Reduced Kick-Back Comparator with Improved Calibration for High-Speed Flash ADCs. - Guy Torfs; Zhisheng Li; Johan Bauwelinck; Xin Yin; Jan Vandewege; Geert Van der Plas (IEICE Trans. Electron., 2009)

A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS. - Julien Ryckaert; Jonathan Borremans; Bob Verbruggen; Lynn Bos; Costantino Armiento; Jan Craninckx; Geert Van der Plas (IEEE J. Solid State Circuits, 2009)

A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS. - Bob Verbruggen; Jan Craninckx; Maarten Kuijk; Piet Wambacq; Geert Van der Plas (IEEE J. Solid State Circuits, 2009)

A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems. - Stephane Bronckers; Karen Scheir; Geert Van der Plas; Gerd Vandersteen; Yves Rolain (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Experimental Analysis of the Coupling Mechanisms Between a 4 GHz PPA and a 5-7 GHz LC -VCO. - Stephane Bronckers; Gerd Vandersteen; Ludwig De Locht; Michael Libois; Geert Van der Plas; Yves Rolain (IEEE Trans. Instrum. Meas., 2009)

Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions. - Geert Van der Plas; Steven Thijs; Dimitri Linten; Guruprasad Katti; Paresh Limaye; Abdelkarim Mercha; Michele Stucchi; Herman Oprins; Bart Vandevelde; Nikolaos Minas; Miro Cupac; Morin Dehan; et al. (CICC, 2010)

A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC ΣΔ modulator in 1.2-V 90-nm CMOS. - Alonso Morgado; Rocío del Río; José M. de la Rosa 001; Lynn Bos; Julien Ryckaert; Geert Van der Plas (ESSCIRC, 2010)

3D integration: Circuit design, test, and reliability challenges. - Nikolaos Minas; Ingrid De Wolf; Erik Jan Marinissen; Michele Stucchi; Herman Oprins; Abdelkarim Mercha; Geert Van der Plas; Dimitrios Velenis; Pol Marchal (IOLTS, 2010)

Design issues and considerations for low-cost 3D TSV IC technology. - Geert Van der Plas; Paresh Limaye; Abdelkarim Mercha; Herman Oprins; Cristina Torregiani; Steven Thijs; Dimitri Linten; Michele Stucchi; Guruprasad Katti; Dimitrios Velenis; Domae Shinichi; Vladimir Cherman; et al. (ISSCC, 2010)

A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS. - Bob Verbruggen; Jan Craninckx; Maarten Kuijk; Piet Wambacq; Geert Van der Plas (ISSCC, 2010)

Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS. - Lynn Bos; Gerd Vandersteen; Pieter Rombouts; Arnd Geis; Alonso Morgado; Yves Rolain; Geert Van der Plas; Julien Ryckaert (IEEE J. Solid State Circuits, 2010)

A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS. - Pieter Crombez; Geert Van der Plas; Michiel Steyaert; Jan Craninckx (IEEE J. Solid State Circuits, 2010)

A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS. - Bob Verbruggen; Jan Craninckx; Maarten Kuijk; Piet Wambacq; Geert Van der Plas (IEEE J. Solid State Circuits, 2010)

Substrate Noise Coupling Mechanisms in Lightly Doped CMOS Transistors. - Stephane Bronckers; Geert Van der Plas; Gerd Vandersteen; Yves Rolain (IEEE Trans. Instrum. Meas., 2010)

In-tier diagnosis of power domains in 3D TSV ICs. - Yuuki Araga; Makoto Nagata; Geert Van der Plas; Jaemin Kim; Nikolaos Minas; Pol Marchal; Youssef Travaly; Michael Libois; Antonio La Manna; Wenqi Zhang; Eric Beyne (3DIC, 2011)

Analysis of microbump induced stress effects in 3D stacked IC technologies. - Andrej Ivankovic; Geert Van der Plas; V. Moroz; M. Choi; Vladimir Cherman; Abdelkarim Mercha; Paul Marchal; Marcel Gonzalez; Geert Eneman; Wenqi Zhang; Thibault Buisson; Mikael Detalle; et al. (3DIC, 2011)

DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow. - Dragomir Milojevic; Herman Oprins; Julien Ryckaert; Paul Marchal; Geert Van der Plas (CICC, 2011)

3D heterogeneous system integration: application driver for 3D technology development. - Eric Beyne; Pol Marchal; Geert Van der Plas (DAC, 2011)

An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations. - Geert Eneman; J. Cho; V. Moroz; Dragomir Milojevic; M. Choi; Kristin De Meyer; Abdelkarim Mercha; Eric Beyne; Thomas Hoffmann 001; Geert Van der Plas (DATE, 2011)

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. - Geert Van der Plas; Paresh Limaye; Igor Loi; Abdelkarim Mercha; Herman Oprins; Cristina Torregiani; Steven Thijs; Dimitri Linten; Michele Stucchi; Guruprasad Katti; Dimitrios Velenis; Vladimir Cherman; et al. (IEEE J. Solid State Circuits, 2011)

Fine grain thermal modeling and experimental validation of 3D-ICs. - Herman Oprins; Adi Srinivasan; Miroslav Cupák; Vladimir Cherman; Cristina Torregiani; Michele Stucchi; Geert Van der Plas; Paul Marchal; Bart Vandevelde; E. Cheng (Microelectron. J., 2011)

Low-Power ADCs for Bio-Medical Applications. - Jan Craninckx; Geert Van der Plas (Bio-Medical CMOS ICs, 2011)

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps. - Wei Guo; Geert Van der Plas; Andrej Ivankovic; Geert Eneman; Vladimir Cherman; Bart De Wachter; Abdelkarim Mercha; Mario Gonzalez; Yann Civale; Augusto Redolfi; Thibault Buisson; A. Jourdan; et al. (ICICDT, 2012)

RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. - Ewout Martens; André Bourdoux; Aïssa Couvreur; Robert Fasthuber; Peter Van Wesemael; Geert Van der Plas; Jan Craninckx; Julien Ryckaert (IEEE J. Solid State Circuits, 2012)

A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS. - Pierluigi Nuzzo 002; Claudio Nani; Costantino Armiento; Alberto L. Sangiovanni-Vincentelli; Jan Craninckx; Geert Van der Plas (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Design issues in heterogeneous 3D/2.5D integration. - Dragomir Milojevic; Pol Marchal; Erik Jan Marinissen; Geert Van der Plas; Diederik Verkest; Eric Beyne (ASP-DAC, 2013)

Session 15 overview: Data converter techniques. - Michael H. Perrott; Geert Van der Plas (ISSCC, 2013)

Analysis of 3D interconnect performance: Effect of the Si substrate resistivity. - X. Sun; Geert Van der Plas; Mikael Detalle; Eric Beyne (3DIC, 2014)

Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges. - Joeri De Vos; Vladimir Cherman; Mikael Detalle; Teng Wang; Abdellah Salahouelhadj; Robert Daily; Geert Van der Plas; Eric Beyne (3DIC, 2014)

Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling. - Bart Vandevelde; Andrej Ivankovic; B. Debecker; Melina Lofrano; Kris Vanstreels; Wei Guo; Vladimir Cherman; Marcel Gonzalez; Geert Van der Plas; Ingrid De Wolf; Eric Beyne; Zsolt Tokei (Microelectron. Reliab., 2014)

Processing active devices on Si interposer and impact on cost. - Dimitrios Velenis; Mikael Detalle; Geert Hellings; Mirko Scholz; Erik Jan Marinissen; Geert Van der Plas; Antonio La Manna; Andy Miller; Dimitri Linten; Eric Beyne (3DIC, 2015)

Through silicon via to FinFET noise coupling in 3-D integrated circuits. - A. Rouhi Najaf Abadi; W. Guo; X. Sun; K. Ben Ali; Jean-Pierre Raskin; Martin Rack; C. Roda Neve; M. Choi; V. Moroz; Geert Van der Plas; Ingrid De Wolf; Eric Beyne; et al. (ICICDT, 2015)

Thermal experimental and modeling analysis of high power 3D packages. - Herman Oprins; Vladimir Cherman; Geert Van der Plas; F. L. T. Maggioni; Joeri De Vos; Eric Beyne (ICICDT, 2015)

Active-lite interposer for 2.5 & 3D integration. - Geert Hellings; Mirko Scholz; Mikael Detalle; Dimitrios Velenis; Muriel de Potter de ten Broeck; C. Roda Neve; Y. Li; Stefaan Van Huylenbroeck; Shih-Hung Chen; Erik Jan Marinissen; Antonio La Manna; Geert Van der Plas; et al. (VLSIC, 2015)

High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer. - C. Roda Neve; Mikael Detalle; Philip Nolmans; Yunlong Li; Joeri De Vos; Geert Van der Plas; Gerald Beyer; Eric Beyne (3DIC, 2016)

TSV process-induced MOS reliability degradation. - Yunlong Li; Michele Stucchi; Stefaan Van Huylenbroeck; Geert Van der Plas; Gerald Beyer; Eric Beyne; Kristof Croes (IRPS, 2018)

A study on substrate noise coupling among TSVs in 3D chip stack. - Yuuki Araga; Makoto Nagata; Joeri De Vos; Geert Van der Plas; Eric Beyne (IEICE Electron. Express, 2018)

Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route. - Giuliano Sisto; Peter Debacker; Rongmei Chen; Geert Van der Plas; Richard Chou; Eric Beyne; Dragomir Milojevic (3DIC, 2019)

Process Complexity and Cost Considerations of Multi-Layer Die Stacks. - Dimitrios Velenis; Joeri De Vos; Soon-Wook Kim; Jaber Derakhshandeh; Pieter Bex; Giovanni Capuz; Samuel Suhard; Kenneth June Rebibis; Stefaan Van Huylenbroeck; Erik Jan Marinissen; Alain Phommahaxay; Andy Miller; et al. (3DIC, 2019)

Comparative Analysis of the Degradation Mechanisms in Logic and I/O FinFET Devices Induced by Plasma Damage. - Gaspard Hiblot; Yefan Liu; Geert Hellings; Geert Van der Plas (IRPS, 2019)

Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited). - Giuliano Sisto; Rongmei Chen; Richard Chou; Geert Van der Plas; Eric Beyne; Rod Metcalfe; Dragomir Milojevic (SLIP, 2021)

Design and Technology Solutions for 3D Integrated High Performance Systems. - Geert Van der Plas; Eric Beyne (VLSI Circuits, 2021)

Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited Paper. - Rongmei Chen; Giuliano Sisto; Odysseas Zografos; Dragomir Milojevic; Pieter Weckx; Geert Van der Plas; Eric Beyne (SLIP, 2022)

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. - Rongmei Chen; Giuliano Sisto; Michele Stucchi; Anne Jourdain; Kenichi Miyaguchi; Pieter Schuddinck; P. Woeltgens; H. Lin; Naveen Kakarla; Anabela Veloso; Dragomir Milojevic; Odysseas Zografos; et al. (VLSI Technology and Circuits, 2022)

(Why do we need) Wireless Heterogeneous Integration (anyway?). - Michaël Peeters; S. Sinha; Xiao Sun; Claude Desset; Giuseppe Gramegna; John Slabbekoorn; Pieter Bex; Nelson Pinho; Tomas Webers; Dimitrios Velenis; Andy Miller; Nadine Collaert; et al. (VLSI Technology and Circuits, 2022)

Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. - Kateryna Serbulova; S.-H. Chen; Geert Hellings; Anabela Veloso; Anne Jourdain; Dimitri Linten; Jo De Boeck; Guido Groeseneken; Julien Ryckaert; Geert Van der Plas; Eric Beyne; Eugenio Dentoni Litta; et al. (VLSI Technology and Circuits, 2022)

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. - Anabela Veloso; Anne Jourdain; D. Radisic; Rongmei Chen; G. Arutchelvan; B. O'Sullivan; Hiroaki Arimura; Michele Stucchi; An De Keersgieter; M. Hosseini; T. Hopf; K. D'Have; et al. (VLSI Technology and Circuits, 2022)

Efficient Backside Power Delivery for High-Performance Computing Systems. - Hesheng Lin; Geert Van der Plas; Xiao Sun; Dimitrios Velenis; Francky Catthoor; Rudy Lauwereins; Eric Beyne (IEEE Trans. Very Large Scale Integr. Syst., 2022)

84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor. - Hesheng Lin; Dimitrios Velenis; Philip Nolmans; Xiao Sun; Francky Catthoor; Rudy Lauwereins; Geert Van der Plas; Eric Beyne (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs. - Mohamed Naeim; Hanqi Yang; Pinhong Chen; Rong Bao; Antoine Dekeyser; Giuliano Sisto; Moritz Brunion; Rongmei Chen; Geert Van der Plas; Eric Beyne; Dragomir Milojevic (3DIC, 2023)

NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips. - Xabier Iturbe; Nassim Abderrahmane; Jaume Abella 001; Sergi Alcaide; Eric Beyne; Henri-Pierre Charles; Christelle Charpin-Nicolle; Lars Chittka; Angélica Dávila; Arne Erdmann; Carles Estrada; Ander Fernández; et al. (DATE, 2023)

Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs). - Subrat Mishra; Sankatali Venkateswarlu; Bjorn Vermeersch; Moritz Brunion; Melina Lofrano; Dawit Burusie Abdi; Herman Oprins; Dwaipayan Biswas; Odysseas Zografos; Gaspard Hiblot; Geert Van der Plas; Pieter Weckx; et al. (IRPS, 2023)

Impact of gate-level clustering on automated system partitioning of 3D-ICs. - Quentin Delhaye; Eric Beyne; Joël Goossens; Geert Van der Plas; Dragomir Milojevic (Microelectron. J., 2023)

Thermal Analysis of 3D Stacking and BEOL Technologies with Functional Partitioning of Many-Core RISC-V SoC. - Mohamed Naeim; Herman Oprins; Sudipta Das; Geert Van der Plas; Yun Dai; Pinhong Chen; CT Kao; Dwaipayan Biswas; Dragomir Milojevic (ISVLSI, 2024)

Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology. - S.-H. Lin; Marko Simicic; N. Pantano; S.-H. Chen; Geert Van der Plas; Eric Beyne; Piet Wambacq (VLSI Technology and Circuits, 2024)