Simulation based Performance Study of Cache Coherence Protocols. - Neethu Bal Mallya; Geeta Patil; Biju K. Raveendran (iNIS, 2015)

Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors. - Neethu Bal Mallya; Geeta Patil; Biju K. Raveendran (VLSID, 2015)

DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems. - Kajal Varma; Geeta Patil; Biju K. Raveendran (VLSID, 2017)

MEDIATOR - A Mixed Criticality Deadline Honored Arbiter for Multi-core Real-time Systems. - Arun S. Nair; Louella Mesquita Colaco; Geeta Patil; Biju K. Raveendran; Sasikumar Punnekkat (DS-RT, 2019)

MOESIF: a MC/MP cache coherence protocol with improved bandwidth utilisation. - Geeta Patil; Neethu Bal Mallya; Biju K. Raveendran (Int. J. Embed. Syst., 2019)

MOESIL: A Cache Coherency Protocol for Locked Mixed Criticality L1 Data Cache. - Arun S. Nair; Aboli Vijayan Pai; Biju K. Raveendran; Geeta Patil (DS-RT, 2021)

CAMP: a hierarchical cache architecture for multi-core mixed criticality processors. - Arun S. Nair; Geeta Patil; Archit Agarwal; Aboli Vijayan Pai; Biju K. Raveendran; Sasikumar Punnekkat (Int. J. Parallel Emergent Distributed Syst., 2024)