Delay Defect Characterization Using Low Voltage Test. - Haihua Yan; Adit D. Singh; Gefu Xu (Asian Test Symposium, 2005)

Low Voltage Test in Place of Fast Clock in DDSI Delay Test. - Haihua Yan; Gefu Xu; Adit D. Singh (ISQED, 2005)

Low Cost Launch-on-Shift Delay Test with Slow Scan Enable. - Gefu Xu; Adit D. Singh (ETS, 2006)

Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. - Adit D. Singh; Gefu Xu (VTS, 2006)

Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan. - Gefu Xu; Adit D. Singh (ATS, 2007)

Achieving high transition delay fault coverage with partial DTSFF scan chains. - Gefu Xu; Adit D. Singh (ITC, 2007)

Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. - Gefu Xu; Adit D. Singh (VLSI Design, 2007)

Scan cell design for launch-on-shift delay tests with slow scan enable. - Gefu Xu; Adit D. Singh (IET Comput. Digit. Tech., 2007)