An experimental 295 MHz CMOS 4K⨉256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers. - Natsuki Kushiyama; Charles Tan; Richard Clark; Jane Lin; Fred Perner; Lisa Martin; Mark Leonard; Gene Coussens; Kit Cham (IEEE J. Solid State Circuits, 1995)