A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. - Hao-I Yang; Shih-Chi Yang; Mao-Chih Hsia; Yung-Wei Lin; Yi-Wei Lin; Chien-Hen Chen; Chi-Shin Chang; Geng-Cing Lin; Yin-Nien Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; et al. (SoCC, 2011)

Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. - Shao-Cheng Wang; Geng-Cing Lin; Yi-Wei Lin; Ming-Chien Tsai; Yi-Wei Chiu; Shyh-Jye Jou; Ching-Te Chuang; Nan-Chun Lien; Wei-Chiang Shih; Kuen-Di Lee; Jyun-Kai Chu (APCCAS, 2012)

An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. - Geng-Cing Lin; Shao-Cheng Wang; Yi-Wei Lin; Ming-Chien Tsai; Ching-Te Chuang; Shyh-Jye Jou; Nan-Chun Lien; Wei-Chiang Shih; Kuen-Di Lee; Jyun-Kai Chu (ISCAS, 2012)

High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. - Hao-I Yang; Yi-Wei Lin; Mao-Chih Hsia; Geng-Cing Lin; Chi-Shin Chang; Yin-Nien Chen; Ching-Te Chuang; Wei Hwang; Shyh-Jye Jou; Nan-Chun Lien; Hung-Yu Li; Kuen-Di Lee; et al. (ISCAS, 2012)

A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. - Yi-Wei Lin; Hao-I Yang; Geng-Cing Lin; Chi-Shin Chang; Ching-Te Chuang; Wei Hwang; Chia-Cheng Chen; Willis Shih; Huan-Shun Huang (ISLPED, 2012)

An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. - Yi-Wei Lin; Ming-Chien Tsai; Hao-I Yang; Geng-Cing Lin; Shao-Cheng Wang; Ching-Te Chuang; Shyh-Jye Jou; Wei Hwang; Nan-Chun Lien; Kuen-Di Lee; Wei-Chiang Shih (VLSI-DAT, 2012)