A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface. - Geng Zhang 001; Fangxu Lv; Zhengbin Pang; Heming Wang; Dongbin Lv; Tao Liu; Jinwang Zhang (ASICON, 2021)

A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication. - Geng Zhang 001; Mingche Lai; Fangxu Lyu; Xuqiang Zheng; Heming Wang; Dongbin Lv; Chaolong Xu; Xingyun Qi; Qing Liu (IEEE Access, 2022)

A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. - Mingche Lai; Geng Zhang 001; Fangxu Lv; Xuqiang Zheng; Heming Wang; Dongbin Lv; Chaolong Xu; Xingyun Qi (Microelectron. J., 2022)

A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks. - Mingche Lai; Fangxu Lv; Geng Zhang 001; Chaolong Xu (HPCC/DSS/SmartCity/DependSys, 2023)

Low-Jitter Retimer Circuits for High-Performance Computer Optical Communications. - Qing Liu; Heming Wang; Fangxu Lv; Geng Zhang 001; Dongbin Lv (ICCEIC, 2023)

A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process. - Wenchen Wang; Fangxu Lv; Zhengbin Pang; Heng Huang; Zhang Luo; Xingyun Qi; Jiaqing Xu; Geng Zhang 001; Kewei Xin; Chengzhuo Zhao (IEICE Electron. Express, 2024)

A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs. - Meng Li; Fangxu Lv; Mingche Lai; Xuqiang Zheng; Heng Huang; Xingyun Qi; Geng Zhang 001 (Microelectron. J., 2024)

A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface. - Bolin Ren; Fangxu Lv; Mingche Lai; Liquan Xiao; Geng Zhang 001; Xuqiang Zheng; Zhang Luo; Jiaqing Xu (Microelectron. J., 2024)

Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator. - Kewei Xin; Mingche Lai; Fangxu Lv; Xuqiang Zheng; Kaile Guo; Zhengbin Pang; Chaolong Xu; Geng Zhang 001; Wenchen Wang; Meng Li (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers. - Chaolong Xu; Fangxu Lv; Mingche Lai; Xingyun Qi; Qiang Wang 006; Zhang Luo; Shijie Li; Geng Zhang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)