Reproducible evaluation of Pan-Tilt-Zoom tracking. - Gengjie Chen; Pierre-Luc St-Charles; Wassim Bouachir; Guillaume-Alexandre Bilodeau; Robert Bergevin (ICIP, 2015)

Reproducible Evaluation of Pan-Tilt-Zoom Tracking. - Gengjie Chen; Pierre-Luc St-Charles; Wassim Bouachir; Thomas Joeisseint; Guillaume-Alexandre Bilodeau; Robert Bergevin (CoRR, 2015)

RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs. - Chak-Wa Pui; Gengjie Chen; Wing-Kai Chow; Ka-Chun Lam; Jian Kuang 001; Peishan Tu; Hang Zhang 010; Evangeline F. Y. Young; Bei Yu 001 (ICCAD, 2016)

Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design. - Gengjie Chen; Jian Kuang 001; Zhiliang Zeng; Hang Zhang 010; Evangeline F. Y. Young; Bei Yu 001 (DAC, 2017)

SALT: Provably good routing topology by a novel steiner shallow-light tree algorithm. - Gengjie Chen; Peishan Tu; Evangeline F. Y. Young (ICCAD, 2017)

Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). - Chak-Wa Pui; Gengjie Chen; Yuzhe Ma; Evangeline F. Y. Young; Bei Yu 001 (ICCAD, 2017)

A two-step search engine for large scale boolean matching under NP3 equivalence. - Chak-Wa Pui; Peishan Tu; Haocheng Li; Gengjie Chen; Evangeline F. Y. Young (ASP-DAC, 2018)

Routability-driven and fence-aware legalization for mixed-cell-height circuits. - Haocheng Li; Wing-Kai Chow; Gengjie Chen; Evangeline F. Y. Young; Bei Yu 001 (DAC, 2018)

RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs. - Gengjie Chen; Chak-Wa Pui; Wing-Kai Chow; Ka-Chun Lam; Jian Kuang 001; Evangeline F. Y. Young; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Detailed routing by sparse grid graph and minimum-area-captured path search. - Gengjie Chen; Chak-Wa Pui; Haocheng Li; Jingsong Chen; Bentian Jiang; Evangeline F. Y. Young (ASP-DAC, 2019)

MARCH: MAze Routing Under a Concurrent and Hierarchical Scheme for Buses. - Jingsong Chen; Jinwei Liu; Gengjie Chen; Dan Zheng; Evangeline F. Y. Young (DAC, 2019)

FIT: Fill Insertion Considering Timing. - Bentian Jiang; Xiaopeng Zhang 009; Ran Chen 001; Gengjie Chen; Peishan Tu; Wei Li 159; Evangeline F. Y. Young; Bei Yu 001 (DAC, 2019)

Dim Sum: Light Clock Tree by Small Diameter Sum. - Gengjie Chen; Evangeline F. Y. Young (DATE, 2019)

Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction. - Haocheng Li; Gengjie Chen; Bentian Jiang; Jingsong Chen; Evangeline F. Y. Young (ICCAD, 2019)

Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search. - Gengjie Chen; Chak-Wa Pui; Haocheng Li; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm. - Gengjie Chen; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Placement for Wafer-Scale Deep Learning Accelerator. - Benzheng Li; Qi Du; Dingcheng Liu; Jingchong Zhang; Gengjie Chen; Hailong You (ASP-DAC, 2021)

TreeNet: Deep Point Cloud Embedding for Routing Tree Construction. - Wei Li 159; Yuxiao Qu; Gengjie Chen; Yuzhe Ma; Bei Yu 001 (ASP-DAC, 2021)

REST: Constructing Rectilinear Steiner Minimum Tree via Reinforcement Learning. - Jinwei Liu; Gengjie Chen; Evangeline F. Y. Young (DAC, 2021)

AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA. - Tingyuan Liang; Gengjie Chen; Jieru Zhao; Sharad Sinha; Wei Zhang 012 (ICCAD, 2021)

Effective and Efficient Detailed Routing with Adaptive Rip-up Scheme and Pin Access Refinement. - Zhongdong Qi; Jingchong Zhang; Gengjie Chen; Hailong You (ACM Great Lakes Symposium on VLSI, 2022)

Pin-Accessible Legalization for Mixed-Cell-Height Circuits. - Haocheng Li; Wing-Kai Chow; Gengjie Chen; Bei Yu 001; Evangeline F. Y. Young (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA. - Tingyuan Liang; Gengjie Chen; Jieru Zhao; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)