Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up. - Gennady Feygin; Patrick Glenn Gulak; Paul Chow (ICASSP, 1991)

Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding. - Gennady Feygin; P. Glenn Gulak; Paul Chow (Data Compression Conference, 1993)

A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. - Gennady Feygin; Paul Chow; P. Glenn Gulak; John Chappel; Grant Goodes; Oswin Hall; Ahmad Sayes; Satwant Singh; Michael B. Smith; Steven J. E. Wilton (ISCAS, 1993)

Architectural tradeoffs for survivor sequence memory management in Viterbi decoders. - Gennady Feygin; Patrick Glenn Gulak (IEEE Trans. Commun., 1993)

A multiprocessor architecture for Viterbi decoders with linear speedup. - Gennady Feygin; Patrick Glenn Gulak; Paul Chow (IEEE Trans. Signal Process., 1993)

Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression. - Gennady Feygin; P. Glenn Gulak; Paul Chow (Data Compression Conference, 1994)

Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding. - Gennady Feygin; P. Glenn Gulak; Paul Chow (Inf. Process. Manag., 1994)

RACER: a reconfigurable constraint-length 14 Viterbi decoder. - David Yeh; Gennady Feygin; Paul Chow (FCCM, 1996)

A 160-MHz analog equalizer for magnetic disk read Channel. - Sami Kiriaki; T. Lakshmi Viswanathan; Gennady Feygin; Robert Bogdan Staszewski; Richard Pierson; Bill Krenik; Michiel de Wit; Krishnaswamy Nagaraj (IEEE J. Solid State Circuits, 1997)

A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation. - Gennady Feygin; Krishnaswamy Nagaraj; Ranjan Chattopadhyay; R. Herrera; I. Papantonopoulos; David A. Martin; P. Wu; Shanthi Pavan (CICC, 2001)

LMS-based calibration of an RF digitally controlled oscillator for mobile phones. - Robert Bogdan Staszewski; John L. Wallberg; Chih-Ming Hung; Gennady Feygin; Mitch Entezari; Dirk Leipold (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A 24mm2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS. - Robert Bogdan Staszewski; Dirk Leipold; Oren E. Eliezer; Mitch Entezari; Khurram Muhammad; Imran Bashir; Chih-Ming Hung; John L. Wallberg; Roman Staszewski; Patrick Cruise; Sameh Rezeq; Sudheer K. Vemulapalli; et al. (ISSCC, 2008)

A 0.8mm2 all-digital SAW-less polar transmitter in 65nm EDGE SoC. - Jaimin Mehta; Robert Bogdan Staszewski; Oren E. Eliezer; Sameh Rezeq; Khurram Waheed; Mitch Entezari; Gennady Feygin; Sudheer K. Vemulapalli; Vasile Zoicas; Chih-Ming Hung; Nathen Barton; Imran Bashir; et al. (ISSCC, 2010)

Relaxed channel polarization for reduced complexity polar coding. - Mostafa El-Khamy; Hessam Mahdavifar; Gennady Feygin; Jungwon Lee; Inyup Kang (WCNC, 2015)

Relaxed Polar Codes. - Mostafa El-Khamy; Hessam Mahdavifar; Gennady Feygin; Jungwon Lee; Inyup Kang (IEEE Trans. Inf. Theory, 2017)