A wafer-scale 170000-gate FFT processor with built-in test circuits. - Koichi Yamashita; Akinori Kanasugi; Shinpei Hijiya; Gensuke Goto; Nobutake Matsumura; Takehide Shirato (IEEE J. Solid State Circuits, 1988)

A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations. - Akira Katsuno; Hiromasa Takahashi; Hajime Kubosawa; Tomio Sato; Atsuhiro Suga; Gensuke Goto (ICCD, 1990)

A Regularly Structured 54-bit Modified-Wallace-Tree Multiplier. - Takao Sato; Masao Nakajima; Takao Sukemura; Gensuke Goto (VLSI, 1991)

An 8.5-ns 112-b transmission gate adder with a conflict-free bypass circuit. - Tomio Sato; Masato Sakate; H. Okada; T. Sukemura; Gensuke Goto (IEEE J. Solid State Circuits, 1992)

A 54*54-b regularly structured tree multiplier. - Gensuke Goto; Tomio Sato; Masao Nakajima; Takao Sukemura (IEEE J. Solid State Circuits, 1992)

Evaluation of fine grain 3-D integrated arithmetic units. - Ryusuke Egawa; Jubee Tada; Hiroaki Kobayashi; Gensuke Goto (3DIC, 2009)

A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers. - Jubee Tada; Ryusuke Egawa; Kazushige Kawai; Hiroaki Kobayashi; Gensuke Goto (3DIC, 2011)

Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating. - Hikaru Tamura; Kiyoshi Kato; Takahiko Ishizu; Tatsuya Onuki; Wataru Uesugi; Takuro Ohmaru; Kazuaki Ohshima; Hidetomo Kobayashi; Seiichi Yoneda; Atsuo Isobe; Naoaki Tsutsui; Suguru Hondo; et al. (COOL Chips, 2014)

A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor. - Atsuo Isobe; Hikaru Tamura; Kiyoshi Kato; Takuro Ohmaru; Wataru Uesugi; Takahiko Ishizu; Tatsuya Onuki; Kazuaki Ohshima; Takanori Matsuzaki; Atsushi Hirose; Yasutaka Suzuki; Naoaki Tsutsui; et al. (VLSIC, 2014)