A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET. - Yohan Frans; Mohamed Elzeftawi; Hiva Hedayati; Jay Im; Vassili Kireev; Toan Pham; Jaewook Shin; Parag Upadhyaya; Lei Zhou; Santiago Asuncion; Chris Borrelli; Geoff Zhang; et al. (VLSI Circuits, 2016)

6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET. - Jay Im; Dave Freitas; Arianne Roldan; Ronan Casey; Stanley Chen; Adam Chou; Tim Cronin; Kevin Geary; Scott McLeod; Lei Zhou; Ian Zhuang; Jaeduk Han; et al. (ISSCC, 2017)

A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET. - Yohan Frans; Jaewook Shin; Lei Zhou; Parag Upadhyaya; Jay Im; Vassili Kireev; Mohamed Elzeftawi; Hiva Hedayati; Toan Pham; Santiago Asuncion; Chris Borrelli; Geoff Zhang; et al. (IEEE J. Solid State Circuits, 2017)

A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET. - Jay Im; Dave Freitas; Arianne Roldan; Ronan Casey; Stanley Chen; Adam Chou; Tim Cronin; Kevin Geary; Scott McLeod; Lei Zhou; Ian Zhuang; Jaeduk Han; et al. (IEEE J. Solid State Circuits, 2017)

A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET. - Parag Upadhyaya; Chi Fung Poon; Siok-Wei Lim; Junho Cho; Arianne Roldan; Wenfeng Zhang; Jin Namkoong; Toan Pham; Bruce Xu; Winson Lin; Hongtao Zhang 002; Nakul Narang; et al. (ISSCC, 2018)

A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET. - Parag Upadhyaya; Chi Fung Poon; Siok-Wei Lim; Junho Cho; Arianne Roldan; Wenfeng Zhang; Jin Namkoong; Toan Pham; Bruce Xu; Winson Lin; Hongtao Zhang 002; Nakul Narang; et al. (IEEE J. Solid State Circuits, 2019)