Holographic Data Storage. - Demetri Psaltis; Geoffrey W. Burr (Computer, 1998)

Holographic data storage technology. - Jonathan J. Ashley; Maria-Pilar Bernal; Geoffrey W. Burr; Hans Coufal; Harald Guenther; John A. Hoffnagle; C. Michael Jefferson; Brian H. Marcus; Roger M. Macfarlane; Robert M. Shelby; Glenn T. Sincerbox (IBM J. Res. Dev., 2000)

Overview of candidate device technologies for storage-class memory. - Geoffrey W. Burr; Bülent N. Kurdi; J. Campbell Scott; Chung Hon Lam; Kailash Gopalakrishnan; Rohit S. Shenoy (IBM J. Res. Dev., 2008)

Phase-change random access memory: A scalable technology. - Simone Raoux; Geoffrey W. Burr; Matthew J. Breitwisch; Charles T. Rettner; Yi-Chou Chen; Robert M. Shelby; Martin Salinga; Daniel Krebs; Shih-Hung Chen; Hsiang-Lan Lung; Chung Hon Lam (IBM J. Res. Dev., 2008)

Nanoscale electronic synapses using phase change devices. - Bryan L. Jackson; Bipin Rajendran; Gregory S. Corrado; Matthew J. Breitwisch; Geoffrey W. Burr; Roger Cheek; Kailash Gopalakrishnan; Simone Raoux; Charles T. Rettner; Alvaro Padilla; Alejandro G. Schrott; Rohit S. Shenoy; et al. (ACM J. Emerg. Technol. Comput. Syst., 2013)

Non-volatile memory as hardware synapse in neuromorphic computing: A first look at reliability issues. - Robert M. Shelby; Geoffrey W. Burr; Irem Boybat; Carmelo di Nolfo (IRPS, 2015)

Large-scale neural networks implemented with Non-Volatile Memory as the synaptic weight element: Impact of conductance response. - Severin Sidler; Irem Boybat; Robert M. Shelby; Pritish Narayanan; Jun-Woo Jang; Alessandro Fumarola; Kibong Moon; Yusuf Leblebici; Hyunsang Hwang; Geoffrey W. Burr (ESSDERC, 2016)

Accelerating machine learning with Non-Volatile Memory: Exploring device and circuit tradeoffs. - Alessandro Fumarola; Pritish Narayanan; Lucas L. Sanches; Severin Sidler; Jun-Woo Jang; Kibong Moon; Robert M. Shelby; Hyunsang Hwang; Geoffrey W. Burr (ICRC, 2016)

Recent Progress in Phase-Change Memory Technology. - Geoffrey W. Burr; Matthew J. BrightSky; Abu Sebastian; Huai-Yu Cheng; Jau-Yi Wu; SangBum Kim; Norma E. Sosa; Nikolaos Papandreou; Hsiang-Lan Lung; Haralampos Pozidis; Evangelos Eleftheriou; Chung Hon Lam (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Circuit-Level Benchmarking of Access Devices for Resistive Nonvolatile Memory Arrays. - Pritish Narayanan; Geoffrey W. Burr; Kumar Virwani; Bülent N. Kurdi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique. - Irem Boybat; Carmelo di Nolfo; Stefano Ambrogio; Martina Bodini; Nathan C. P. Farinha; Robert M. Shelby; Pritish Narayanan; Severin Sidler; Hsinyu Tsai; Yusuf Leblebici; Geoffrey W. Burr (ICRC, 2017)

Neuromorphic devices and architectures for next-generation cognitive computing. - Geoffrey W. Burr; Pritish Narayanan; Robert M. Shelby; Stefano Ambrogio; Hsinyu Tsai; Scott L. Lewis; Kohji Hosokawa (ISCAS, 2017)

Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays. - Pritish Narayanan; Lucas L. Sanches; Alessandro Fumarola; Robert M. Shelby; Stefano Ambrogio; Jun-Woo Jang; Hyunsang Hwang; Yusuf Leblebici; Geoffrey W. Burr (ISCAS, 2017)

Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory. - Pritish Narayanan; Alessandro Fumarola; Lucas L. Sanches; Kohji Hosokawa; Scott C. Lewis; Robert M. Shelby; Geoffrey W. Burr (IBM J. Res. Dev., 2017)

Equivalent-accuracy accelerated neural-network training using analogue memory. - Stefano Ambrogio; Pritish Narayanan; Hsinyu Tsai; Robert M. Shelby; Irem Boybat; Carmelo di Nolfo; Severin Sidler; Massimo Giordano; Martina Bodini; Nathan C. P. Farinha; Benjamin Killeen; Christina Cheng; et al. (Nat., 2018)

Reliability Challenges with Materials for Analog Computing. - Eduard A. Cartier; Wanki Kim; Nanbo Gong; Tayfun Gokmen; Martin M. Frank; Douglas M. Bishop; Youngseok Kim; Seyoung Kim; Takashi Ando; Ernest Y. Wu; Praneet Adusumilli; John Rozen; et al. (IRPS, 2019)

Non-filamentary non-volatile memory elements as synapses in neuromorphic systems. - Alessandro Fumarola; Yusuf Leblebici; Pritish Narayanan; Robert M. Shelby; L. L. Sanchez; Geoffrey W. Burr; Kibong Moon; J. Jang; Hyunsang Hwang; Severin Sidler (NVMTS, 2019)

Analog-to-Digital Conversion With Reconfigurable Function Mapping for Neural Networks Activation Function Acceleration. - Massimo Giordano; Giorgio Cristiano; Koji Ishibashi; Stefano Ambrogio; Hsinyu Tsai; Geoffrey W. Burr; Pritish Narayanan (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed. - Hung-Yang Chang; Pritish Narayanan; Scott C. Lewis; Nathan C. P. Farinha; Kohji Hosokawa; Charles Mackin; Hsinyu Tsai; Stefano Ambrogio; An Chen 002; Geoffrey W. Burr (IBM J. Res. Dev., 2019)

A role for analogue memory in AI hardware. - Geoffrey W. Burr (Nat. Mach. Intell., 2019)

Accelerating Deep Neural Networks with Analog Memory Devices. - Stefano Ambrogio; Pritish Narayanan; Hsinyu Tsai; Charles Mackin; Katherine Spoon; An Chen 002; Andrea Fasoli; Alexander M. Friz; Geoffrey W. Burr (AICAS, 2020)

Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges. - Charles Mackin; Pritish Narayanan; Stefano Ambrogio; Hsinyu Tsai; Katie Spoon; Andrea Fasoli; An Chen 002; Alexander M. Friz; Robert M. Shelby; Geoffrey W. Burr (IRPS, 2020)

Optimization of Analog Accelerators for Deep Neural Networks Inference. - Andrea Fasoli; Stefano Ambrogio; Pritish Narayanan; Hsinyu Tsai; Charles Mackin; Katherine Spoon; Alexander M. Friz; An Chen 002; Geoffrey W. Burr (ISCAS, 2020)

Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation. - Robert L. Bruce; Syed Ghazi Sarwat; Irem Boybat; Cheng-Wei Cheng; Wanki Kim; S. R. Nandakumar; Charles Mackin; Timothy Philip; Zuoguang Liu; Kevin Brew; Nanbo Gong; Injo Ok; et al. (IRPS, 2021)

Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited). - Kohji Hosokawa; Pritish Narayanan; Stefano Ambrogio; Hsinyu Tsai; Charles Mackin; Andrea Fasoli; Alexander M. Friz; An Chen 002; Jose Luquin; Katherine Spoon; Geoffrey W. Burr; Scott C. Lewis (ISCAS, 2021)

Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices. - Katie Spoon; Hsinyu Tsai; An Chen 002; Malte J. Rasch; Stefano Ambrogio; Charles Mackin; Andrea Fasoli; Alexander M. Friz; Pritish Narayanan; Milos Stanisavljevic; Geoffrey W. Burr (Frontiers Comput. Neurosci., 2021)

Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers. - Atsuya Okazaki; Pritish Narayanan; Stefano Ambrogio; Kohji Hosokawa; Hsinyu Tsai; Akiyo Nomura; Takeo Yasuda; Charles Mackin; Alexander M. Friz; Masatoshi Ishii; Yasuteru Kohda; Katie Spoon; et al. (ISCAS, 2022)

Fair and Comprehensive Benchmarking of Machine Learning Processing Chips. - Geoffrey W. Burr; Sukhwan Lim; Boris Murmann; Rangharajan Venkatesan; Marian Verhelst (IEEE Des. Test, 2022)

Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited). - Martin M. Frank; Ning Li; Malte J. Rasch; Shubham Jain; Ching-Tzu Chen; Ramachandran Muralidhar; Jin-Ping Han; Vijay Narayanan; Timothy Philip; Kevin Brew; Andrew Simon; Iqbal Saraf; et al. (IRPS, 2023)

Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited). - Hsinyu Tsai; Pritish Narayanan; Shubham Jain; Stefano Ambrogio; Kohji Hosokawa; Masatoshi Ishii; Charles Mackin; Ching-Tzu Chen; Atsuya Okazaki; Akiyo Nomura; Irem Boybat; Ramachandran Muralidhar; et al. (ISCAS, 2023)

Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited). - Geoffrey W. Burr; Pritish Narayanan; Stefano Ambrogio; Atsuya Okazaki; Hsinyu Tsai; Kohji Hosokawa; Charles Mackin; Akiyo Nomura; Takeo Yasuda; J. Demarest; Kevin Brew; Victor Chan; et al. (VLSI Technology and Circuits, 2023)

Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators. - Malte J. Rasch; Charles Mackin; Manuel Le Gallo; An Chen 002; Andrea Fasoli; Frédéric Odermatt; Ning Li; S. R. Nandakumar; Pritish Narayanan; Hsinyu Tsai; Geoffrey W. Burr; Abu Sebastian; et al. (CoRR, 2023)

An analog-AI chip for energy-efficient speech recognition and transcription. - Stefano Ambrogio; Pritish Narayanan; Atsuya Okazaki; Andrea Fasoli; Charles Mackin; Kohji Hosokawa; Akiyo Nomura; Takeo Yasuda; An Chen 002; Alexander M. Friz; Masatoshi Ishii; Jose Luquin; et al. (Nat., 2023)

A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh. - Shubham Jain; Hsinyu Tsai; Ching-Tzu Chen; Ramachandran Muralidhar; Irem Boybat; Martin M. Frank; Stanislaw Wozniak; Milos Stanisavljevic; Praneet Adusumilli; Pritish Narayanan; Kohji Hosokawa; Masatoshi Ishii; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Analog-AI Hardware Accelerators for Low-Latency Transformer-Based Language Models (Invited). - Geoffrey W. Burr; H. Tsai; Irem Boybat; William Andrew Simon; Julian Büchel; Athanasios Vasilopoulos; Pritish Narayanan; Andrea Fasoli; Kohji Hosokawa; Manuel Le Gallo; M. Ishii; Yasuteru Kohda; et al. (CICC, 2025)

NORA: Noise-Optimized Rescaling of LLMs on Analog Compute-in-Memory Accelerators. - Yayue Hou; Hsinyu Tsai; Kaoutar El Maghraoui; Tayfun Gokmen; Geoffrey W. Burr; Liu Liu (DATE, 2025)

Analog AI Accelerators for Transformer-based Language Models: Hardware, Workload, and Power Performance. - H. Tsai; Hadjer Benmeziane; Irem Boybat; Julian Büchel; Pritish Narayanan; Manuel Le Gallo; S. Jain; Athanasios Vasilopoulos; W. Simon; Kohji Hosokawa; M. Ishii; Yasuteru Kohda; et al. (IMW, 2025)

Efficient scaling of large language models with mixture of experts and 3D analog in-memory computing. - Julian Büchel; Athanasios Vasilopoulos; William Andrew Simon; Irem Boybat; Hsinyu Tsai; Geoffrey W. Burr; Hernan Castro; Bill Filipiak; Manuel Le Gallo; Abbas Rahimi; Vijay Narayanan; Abu Sebastian (Nat. Comput. Sci., 2025)

Rapid yet accurate Tile-circuit and device modeling for Analog In-Memory Computing. - Jose Luquin; Charles Mackin; Stefano Ambrogio; An Chen 002; F. Baldi; G. Miralles; Malte J. Rasch; Julian Büchel; M. Lalwani; W. Ponghiran; Paul Solomon; Hsinyu Tsai; et al. (CoRR, 2025)

CiMBA: Accelerating Genome Sequencing Through On-Device Basecalling via Compute-in-Memory. - William Andrew Simon; Irem Boybat; Riselda Kodra; Elena Ferro; Gagandeep Singh 002; Mohammed Alser; Shubham Jain; Hsinyu Tsai; Geoffrey W. Burr; Onur Mutlu; Abu Sebastian (IEEE Trans. Parallel Distributed Syst., 2025)