BSIM4-based lateral diode model for LNA co-designed with ESD protection circuit. - Ming-Ta Yang; Yang Du; Charles Teng; Tony Chang; Eugene Worley; Ken Liao; You-Wen Yau; Geoffrey Yeap (ISQED, 2010)

FinFET based SRAM bitcell design for 32 nm node and below. - Seung Chul Song; M. Abu-Rahma; Geoffrey Yeap (Microelectron. J., 2011)

Technology-design-manufacturing co-optimization for advanced mobile SoCs. - Geoffrey Yeap (CICC, 2014)

Improved device variability in scaled MOSFETs with deeply retrograde channel profile. - Jason Woo; Po-Yen Chien; Frank Yang; Seung Chul Song; P. R. Chidi Chidambaram; Joseph Wang 002; Geoffrey Yeap (Microelectron. Reliab., 2014)

Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization. - N. N. Mojumder; Seung Chul Song; K. Rim; J. Xu; Joseph Wang; J. Zhu; Milena Vratonjic; K. Lin; Martin Saint-Laurent; Paul Bassett; Geoffrey Yeap (VLSIC, 2015)

Holistic technology optimization and key enablers for 7nm mobile SoC. - Seung Chul Song; J. Xu; N. N. Mojumder; K. Rim; D. Yang; Jerry Bao; J. Zhu; Joseph Wang; Mustafa Badaroglu; V. Machkaoutsan; Praneeth Narayanasetti; B. Bucki; et al. (VLSIC, 2015)

SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit. - Younghwi Yang; Juhyun Park; Seung Chul Song; Joseph Wang; Geoffrey Yeap; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology. - Younghwi Yang; Juhyun Park; Seung Chul Song; Joseph Wang; Geoffrey Yeap; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2015)

-197dBc/Hz FOM 4.3-GHz VCO Using an addressable array of minimum-sized nmos cross-coupled transistor pairs in 65-nm CMOS. - Amit Jha; Ali Ahmadi; Sandeep Kshattry; T. Cao; K. Liao; Geoffrey Yeap; Yiorgos Makris; Kenneth K. O (VLSI Circuits, 2016)

Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes. - Seung Chul Song; J. Xu; D. Yang; K. Rim; P. Feng; Jerry Bao; J. Zhu; Joseph Wang; G. Nallapati; Mustafa Badaroglu; Praneeth Narayanasetti; B. Bucki; et al. (VLSI Circuits, 2016)

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology. - Younghwi Yang; Hanwool Jeong; Seung Chul Song; Joseph Wang; Geoffrey Yeap; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. - Jonathan Chang; Yen-Huei Chen; Gary Chan; Hank Cheng; Po-Sheng Wang; Yangsyu Lin; Hidehiro Fujiwara; Robin Lee; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li (ISSCC, 2020)

A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; Wei-Min Chan; Hank Cheng; Po-Sheng Wang; Yangsyu Lin; Hidehiro Fujiwara; Robin Lee; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li (IEEE J. Solid State Circuits, 2021)

A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology. - Nick Zhang; Young Suk Kim; Peter Hsu; Samsoo Kim; Derek Tao; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)

A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; K. Venkateswara Reddy; Nikhil Puri; Teja Masina; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; Ku-Feng Lin; et al. (ISSCC, 2025)