Current conveyor based amplifier and adaptive buffer for use in an analog frontend. - Georg Ellguth; Stephan Henker; Christian Mayr 001; René Schüffny (ICECS, 2009)

Low power design of the X-GOLD® SDR 20 baseband processor. - Wolfgang Raab; Jörg Berthold; J. A. Ulrich Hachmann; Dominik Langen; Michael Schreiner; Holger Eisenreich; Jens-Uwe Schluessler; Georg Ellguth (DATE, 2010)

A low-power cell-based-design multi-port register file in 65nm CMOS technology. - Johannes Uhlig; Sebastian Höppner; Georg Ellguth; René Schüffny (ISCAS, 2010)

Mismatch characterization of high-speed NoC links using asynchronous sub-sampling. - Sebastian Höppner; Dennis Walter; Georg Ellguth; René Schüffny (SoC, 2011)

A power management architecture for fast per-core DVFS in heterogeneous MPSoCs. - Sebastian Höppner; Chenming Shao; Holger Eisenreich; Georg Ellguth; Mario Ander; René Schüffny (ISCAS, 2012)

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS. - Dennis Walter; Sebastian Höppner; Holger Eisenreich; Georg Ellguth; Stephan Henker; Stefan Hänzsche; René Schüffny; Markus Winter 002; Gerhard P. Fettweis (ISSCC, 2012)

A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates. - Markus Winter 002; Steffen Kunze; Esther P. Adeva; Björn Mennenga; Emil Matús; Gerhard P. Fettweis; Holger Eisenreich; Georg Ellguth; Sebastian Höppner; Stefan Scholze; René Schüffny; Tomoyoshi Kobori (ISSCC, 2012)

On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links. - Sebastian Höppner; Dennis Walter; Georg Ellguth; René Schüffny (Int. J. Embed. Real Time Commun. Syst., 2012)

A 32 GBit/s communication SoC for a waferscale neuromorphic system. - Stefan Scholze; Holger Eisenreich; Sebastian Höppner; Georg Ellguth; Stephan Henker; Mario Ander; Stefan Hänzsche; Johannes Partzsch; Christian Mayr 001; René Schüffny (Integr., 2012)

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology. - Sebastian Höppner; Stefan Hänzsche; Georg Ellguth; Dennis Walter; Holger Eisenreich; René Schüffny (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology. - Sebastian Höppner; Holger Eisenreich; Stephan Henker; Dennis Walter; Georg Ellguth; René Schüffny (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A compact on-chip IR-drop measurement system in 28 nm CMOS technology. - Sebastian Dietel; Sebastian Höppner; Holger Eisenreich; Georg Ellguth; Stefan Hänzsche; Stephan Henker; René Schüffny; Tim Brauninger; Ulrich Fiedler (ISCAS, 2014)

10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS. - Benedikt Noethen; Oliver Arnold; Esther P. Adeva; Tobias Seifert; Erik Fischer; Steffen Kunze; Emil Matús; Gerhard P. Fettweis; Holger Eisenreich; Georg Ellguth; Stephan Hartmann 002; Sebastian Höppner; et al. (ISSCC, 2014)

Switched-Capacitor Realization of Presynaptic Short-Term-Plasticity and Stop-Learning Synapses in 28 nm CMOS. - Marko Noack; Johannes Partzsch; Christian Mayr 001; Stefan Hänzsche; Stefan Scholze; Sebastian Höppner; Georg Ellguth; René Schüffny (CoRR, 2014)

A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology. - Stefan Hänzsche; Sebastian Höppner; Georg Ellguth; René Schüffny (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS. - Sebastian Höppner; Dennis Walter; Thomas Hocker; Stephan Henker; Stefan Hänzsche; Daniel Sausner; Georg Ellguth; Jens-Uwe Schluessler; Holger Eisenreich; René Schüffny (IEEE J. Solid State Circuits, 2015)

An MPSoC for energy-efficient database query processing. - Sebastian Haas; Oliver Arnold; Benedikt Nöthen; Stefan Scholze; Georg Ellguth; Andreas Dixius; Sebastian Höppner; Stefan Schiefer; Stephan Hartmann 002; Stephan Henker; Thomas Hocker; Jörg Schreiter; et al. (DAC, 2016)

A database accelerator for energy-efficient query processing and optimization. - Sebastian Haas; Oliver Arnold; Stefan Scholze; Sebastian Höppner; Georg Ellguth; Andreas Dixius; Annett Ungethüm; Eric Mier; Benedikt Noethen; Emil Matús; Stefan Schiefer; Love Cederstroem; et al. (NORCAS, 2016)

A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits. - Christian Mayr 001; Johannes Partzsch; Marko Noack; Stefan Hänzsche; Stefan Scholze; Sebastian Höppner; Georg Ellguth; René Schüffny (IEEE Trans. Biomed. Circuits Syst., 2016)

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications. - Sebastian Haas; Tobias Seifert; Benedikt Nöthen; Stefan Scholze; Sebastian Höppner; Andreas Dixius; Esther Pérez Adeva; Thomas R. Augustin; Friedrich Pauls; Sadia Moriam; Mattis Hasler; Erik Fischer; et al. (DAC, 2017)

Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems. - Sebastian Höppner; Yexin Yan; Bernhard Vogginger; Andreas Dixius; Johannes Partzsch; Prateek Joshi; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Stefan Scholze; Georg Ellguth; Love Cederstroem; et al. (ISCAS, 2017)

Dynamic voltage and frequency scaling for neuromorphic many-core systems. - Sebastian Höppner; Yexin Yan; Bernhard Vogginger; Andreas Dixius; Johannes Partzsch; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Stefan Scholze; Georg Ellguth; Love Cederstroem; Matthias Eberlein; et al. (ISCAS, 2017)

Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS. - Florian Protze; Martin Kreißig; Frank Ellinger; Sebastian Höppner; Stephan Hartmann 002; Stefan Hänzsche; Stefan Scholze; Georg Ellguth; Christian Mayr 001 (VLSI-SoC, 2019)

Dynamic Power Management for Neuromorphic Many-Core Systems. - Sebastian Höppner; Bernhard Vogginger; Yexin Yan; Andreas Dixius; Stefan Scholze; Johannes Partzsch; Felix Neumärker; Stephan Hartmann 002; Stefan Schiefer; Georg Ellguth; Love Cederstroem; Luis A. Plana; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing. - Sebastian Höppner; Yexin Yan; Andreas Dixius; Stefan Scholze; Johannes Partzsch; Marco Stolba; Florian Kelber; Bernhard Vogginger; Felix Neumärker; Georg Ellguth; Stephan Hartmann 002; Stefan Schiefer; et al. (CoRR, 2021)

Hardware Implementation of an OPC UA Server for Industrial Field Devices. - Heiner Bauer; Sebastian Höppner; Chris Paul Iatrou; Zohra Charania; Stephan Hartmann 002; Saif-Ur Rehman; Andreas Dixius; Georg Ellguth; Dennis Walter; Johannes Uhlig; Felix Neumärker; Marc Berthel; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 16-Channel Fully Configurable Neural SoC With 1.52 $ mu$W/Ch Signal Acquisition, 2.79 $ mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI. - Seyed Mohammad Ali Zeinolabedin; Franz Marcus Schüffny; Richard George 001; Florian Kelber; Heiner Bauer; Stefan Scholze; Stefan Hänzsche; Marco Stolba; Andreas Dixius; Georg Ellguth; Dennis Walter; Sebastian Höppner; et al. (IEEE Trans. Biomed. Circuits Syst., 2022)

EdgeVision SoC: PPA-Impact of RTL-level Modifications. - Mikail Yayla; Clifford Leon Dmello; Georg Ellguth; Uwe Steeb; Tim Leuchter; Marcus Pietzsch; Holger Eisenreich (SOCC, 2024)