Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes. - Stephan Henzler; Markus Koban; Doris Schmitt-Landsiedel; Jörg Berthold; Georg Georgakos (VLSI-SOC, 2003)

Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes. - Stephan Henzler; Philip Teichmann; Markus Koban; Jörg Berthold; Georg Georgakos; Doris Schmitt-Landsiedel (VLSI-SoC (Selected Papers), 2003)

Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption. - Stephan Henzler; Georg Georgakos; Jörg Berthold; Doris Schmitt-Landsiedel (PATMOS, 2004)

Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits. - Stephan Henzler; Georg Georgakos; Jörg Berthold; Doris Schmitt-Landsiedel (PATMOS, 2004)

Dynamic state-retention flip flop for fine-grained sleep-transistor scheme. - Stephan Henzler; Thomas Nirschi; Christian Pacha; Peter Spindler; Philip Teichmann; Michael Fulde; Jürgen Fischer; Matthias Eireiner; Thomas Fischer; Georg Georgakos; Jörg Berthold; Doris Schmitt-Landsiedel (ESSCIRC, 2005)

A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions. - Thomas Lüftner; Jörg Berthold; Christian Pacha; Georg Georgakos; Guillaume Sauzon; Olaf Hömke; Jurij Beshenar; Peter Mahrla; Knut M. Just; Peter Hober; Stephan Henzler; Doris Schmitt-Landsiedel; et al. (ISSCC, 2006)

Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead. - Stephan Henzler; Georg Georgakos; Matthias Eireiner; Thomas Nirschl; Christian Pacha; Jörg Berthold; Doris Schmitt-Landsiedel (IEEE J. Solid State Circuits, 2006)

Layout options for stability tuning of SRAM cells in multi-gate-FET technologies. - Florian Bauer; Klaus von Arnim; Christian Pacha; Thomas Schulz; Michael Fulde; Axel Nackaerts; M. Jurczak; Wade Xiong; K. T. San; C. Rinn Cleavelin; Klaus Schruefer; Georg Georgakos; et al. (ESSCIRC, 2007)

Soft Error Rates in 65nm SRAMs–Analysis of new Phenomena. - Franz X. Ruckerbauer; Georg Georgakos (IOLTS, 2007)

In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations. - Matthias Eireiner; Stephan Henzler; Georg Georgakos; Jörg Berthold; Doris Schmitt-Landsiedel (IEEE J. Solid State Circuits, 2007)

A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions. - Thomas Lüftner; Jörg Berthold; Christian Pacha; Georg Georgakos; Guillaume Sauzon; Olaf Hömke; Jurij Beshenar; Peter Mahrla; Knut M. Just; Peter Hober; Stephan Henzler; Doris Schmitt-Landsiedel; et al. (IEEE J. Solid State Circuits, 2007)

A Design Space Comparison of 6T and 8T SRAM Core-Cells. - Florian Bauer; Georg Georgakos; Doris Schmitt-Landsiedel (PATMOS, 2008)

Fast stability analysis of large-scale SRAM arrays and the impact of NBTI degradation. - Stefan Drapatz; Thomas Fischer; Karl Hofmann; Ettore Amirante; Peter Huber; Martin Ostermayr; Georg Georgakos; Doris Schmitt-Landsiedel (ESSCIRC, 2009)

Aging analysis of circuit timing considering NBTI and HCI. - Dominik Lorenz; Georg Georgakos; Ulf Schlichtmann (IOLTS, 2009)

Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level (Alterungsanalyse von kombinatorischen Schaltungen auf Gatterebene). - Dominik Lorenz; Georg Georgakos; Ulf Schlichtmann (it Inf. Technol., 2010)

A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring. - Martin Wirnshofer; Leonhard Heiß; Georg Georgakos; Doris Schmitt-Landsiedel (DDECS, 2011)

Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit. - Martin Wirnshofer; Leonhard Heiß; Anil Narayan Kakade; Nasim Pour Aryan; Georg Georgakos; Doris Schmitt-Landsiedel (DDECS, 2012)

On-Line Supply voltage Scaling Based on in situ Delay Monitoring to Adapt for Pvta variations. - Martin Wirnshofer; Nasim Pour Aryan; Leonhard Heiß; Doris Schmitt-Landsiedel; Georg Georgakos (J. Circuits Syst. Comput., 2012)

Reliability challenges for electric vehicles: from devices to architecture and systems software. - Georg Georgakos; Ulf Schlichtmann; Reinhard Schneider 001; Samarjit Chakraborty (DAC, 2013)

Reliability monitoring of digital circuits by in situ timing measurement. - Nasim Pour Aryan; Georg Georgakos; Doris Schmitt-Landsiedel (PATMOS, 2013)

From an analytic NBTI device model to reliability assessment of complex digital circuits. - Nasim Pour Aryan; A. Listl; Leonhard Heiß; Cenk Yilmaz; Georg Georgakos; Doris Schmitt-Landsiedel (IOLTS, 2014)

Power efficient digital IC design for a medical application with high reliability requirements. - Nasim Pour Aryan; Nils Heidmann; Martin Wirnshofer; Nico Hellwege; Jonas Pistor; Dagmar Peters-Drolshagen; Georg Georgakos; Steffen Paul; Doris Schmitt-Landsiedel (PATMOS, 2014)

A fWLR test structure and method for device reliability monitoring using product relevant circuits. - Rolf-Peter Vollertsen; Georg Georgakos; K. Kölpin; C. Olk (IRPS, 2015)

In situ measurement of aging-induced performance degradation in digital circuits. - Nasim Pour Aryan; Christian Funke; Jens Bargfrede; Cenk Yilmaz; Doris Schmitt-Landsiedel; Georg Georgakos (ETS, 2016)

A new 3-bit burst-error correcting code. - Alexander Klockmann; Georg Georgakos; Michael Gössel (IOLTS, 2017)

From Device Aging Physics to Automated Circuit Reliability Sign Off. - Christian Schlünder; Katja Waschneck; Peter Rotter; Susanne Lachenmann; Hans Reisinger; Franz Ungar; Georg Georgakos (IRPS, 2019)