GORDIAN: a new global optimization/rectangle dissection method for cell placement. - Jürgen M. Kleinhans; Georg Sigl; Frank M. Johannes (ICCAD, 1988)

Analytical Placement: A Linear or a Quadratic Objective Function? - Georg Sigl; Konrad Doll; Frank M. Johannes (DAC, 1991)

Goal oriented slicing enumeration through shape function clipping. - Georg Sigl; Ulf Schlichtmann (EURO-DAC, 1991)

A New Linear Placement Algorithm for Cell Generation. - Edgar Auer; Werner L. Schiele; Georg Sigl (ICCAD, 1991)

DOMINO: Deterministic Placement Improvement with Hill-Climbing Capabilities. - Konrad Doll; Frank M. Johannes; Georg Sigl (VLSI, 1991)

GORDIAN: VLSI placement by quadratic programming and slicing optimization. - Jürgen M. Kleinhans; Georg Sigl; Frank M. Johannes; Kurt Antreich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Parallel algorithms for slicing based final placement. - Henning Spruth; Georg Sigl (EURO-DAC, 1992)

Accurate net models for placement improvement by network flow methods. - Konrad Doll; Frank M. Johannes; Georg Sigl (ICCAD, 1992)

Plazierung der Zellen bei der Layoutsynthese mittels Partitionierung und quadratischer Optimierung. - Georg Sigl (1992)

Parallel algorithms for slicing based final placement - Henning Spruth; Georg Sigl; Frank Johannes (Forschungsberichte, TU Munich, 1992)

A Cost-Effective FPGA-based Fault Simulation Environment. - Angelika Janning; Johann Heyszl; Frederic Stumpf; Georg Sigl (FDTC, 2011)

Keynote address: Design of secure systems - Where are the EDA tools? - Georg Sigl (ICCAD, 2011)

Side-Channel Analysis of PUFs and Fuzzy Extractors. - Dominik Merli; Dieter Schuster; Frederic Stumpf; Georg Sigl (TRUST, 2011)

Reliability bound and channel capacity of IBS-based fuzzy embedders. - Matthias Hiller; Fabrizio De Santis; Dominik Merli; Georg Sigl (AHS, 2012)

Strengths and Limitations of High-Resolution Electromagnetic Field Measurements for Side-Channel Analysis. - Johann Heyszl; Dominik Merli; Benedikt Heinz; Fabrizio De Santis; Georg Sigl (CARDIS, 2012)

Localized Electromagnetic Analysis of Cryptographic Implementations. - Johann Heyszl; Stefan Mangard; Benedikt Heinz; Frederic Stumpf; Georg Sigl (CT-RSA, 2012)

Complementary IBS: Application specific error correction for PUFs. - Matthias Hiller; Dominik Merli; Frederic Stumpf; Georg Sigl (HOST, 2012)

Detection of probing attempts in secure ICs. - Salvador Manich; Markus S. Wamser; Georg Sigl (HOST, 2012)

Physical Unclonable Functions. - Dominik Merli; Georg Sigl (Datenschutz und Datensicherheit, 2012)

Identities for Embedded Systems Enabled by Physical Unclonable Functions. - Dominik Merli; Georg Sigl; Claudia Eckert 001 (Number Theory and Cryptography, 2013)

Breaking through fixed PUF block limitations with differential sequence coding and convolutional codes. - Matthias Hiller; Michael Weiner 004; Leandro Rodrigues Lima; Maximilian Birkner; Georg Sigl (TrustED@CCS, 2013)

Comprehensive analysis of software countermeasures against fault attacks. - Nikolaus Theißing; Dominik Merli; Michael Smola; Frederic Stumpf; Georg Sigl (DATE, 2013)

Localized electromagnetic analysis of RO PUFs. - Dominik Merli; Johann Heyszl; Benedikt Heinz; Dieter Schuster; Frederic Stumpf; Georg Sigl (HOST, 2013)

On the Relationship between Correlation Power Analysis and the Stochastic Approach: An ASIC Designer Perspective. - Fabrizio De Santis; Michael Kasper; Stefan Mangard; Georg Sigl; Oliver Stein; Marc Stöttinger (INDOCRYPT, 2013)

Differential scan-path: A novel solution for secure design-for-testability. - Salvador Manich; Markus S. Wamser; Oscar M. Guillen; Georg Sigl (ITC, 2013)

A new model for estimating bit error probabilities of Ring-Oscillator PUFs. - Matthias Hiller; Georg Sigl; Michael Pehl (ReCoSoC, 2013)

Clustering Algorithms for Non-Profiled Single-Execution Attacks on Exponentiations. - Johann Heyszl; Andreas Ibing; Stefan Mangard; Fabrizio De Santis; Georg Sigl (IACR Cryptol. ePrint Arch., 2013)

Protecting PUF Error Correction by Codeword Masking. - Dominik Merli; Frederic Stumpf; Georg Sigl (IACR Cryptol. ePrint Arch., 2013)

Risk management in embedded devices using metering applications as example. - Oscar M. Guillen; Ralf Brederlow; Ralph Ledwa; Georg Sigl (WESS, 2014)

Increasing the efficiency of syndrome coding for PUFs with helper data compression. - Matthias Hiller; Georg Sigl (DATE, 2014)

Seesaw: An Area-Optimized FPGA Viterbi Decoder for PUFs. - Matthias Hiller; Leandro Rodrigues Lima; Georg Sigl (DSD, 2014)

Closing the Gap between Speed and Configurability of Multi-bit Fault Emulation Environments for Security and Safety-Critical Designs. - Ralph Nyberg; Jürgen Nolles; Johann Heyszl; Dirk Rabe; Georg Sigl (DSD, 2014)

On MILS I/O Sharing Targeting Avionic Systems. - Kevin Mueller; Georg Sigl; Benoit Triquet; Michael Paulitsch (EDCC, 2014)

On Cache Timing Attacks Considering Multi-core Aspects in Virtualized Embedded Systems. - Michael Weiß; Benjamin Weggenmann; Moritz August; Georg Sigl (INTRUST, 2014)

Reconfigurable PUFs for FPGA-based SoCs. - Stefan Gehrer; Georg Sigl (ISIC, 2014)

Investigating measurement methods for high-resolution electromagnetic field side-channel analysis. - Robert Specht; Johann Heyszl; Georg Sigl (ISIC, 2014)

Ciphertext-Only Fault Attacks on PRESENT. - Fabrizio De Santis; Oscar M. Guillen; Ermin Sakic; Georg Sigl (LightSec, 2014)

A Low Area Probing Detector for Power Efficient Security ICs. - Michael Weiner 004; Salvador Manich; Georg Sigl (RFIDSec, 2014)

Error Correction for Physical Unclonable Functions Using Generalized Concatenated Codes. - Sven Müelich; Sven Puchinger; Martin Bossert; Matthias Hiller; Georg Sigl (CoRR, 2014)

Hardware Trojans: current challenges and approaches. - Nisha Jacob; Dominik Merli; Johann Heyszl; Georg Sigl (IET Comput. Digit. Tech., 2014)

A Lightweight Framework for Cold Boot Based Forensics on Mobile Devices. - Benjamin Taubmann; Manuel Huber 001; Sascha Wessel; Lukas Heim; Hans Peter Reiser; Georg Sigl (ARES, 2015)

seTPM: Towards Flexible Trusted Computing on Mobile Devices Based on GlobalPlatform Secure Elements. - Sergej Proskurin; Michael Weiß; Georg Sigl (CARDIS, 2015)

Precise Laser Fault Injections into 90 nm and 45 nm SRAM-cells. - Bodo Selmke; Stefan Brummer; Johann Heyszl; Georg Sigl (CARDIS, 2015)

Side Channel Attacks on Smartphones and Embedded Devices Using Standard Radio Equipment. - Gabriel Goller; Georg Sigl (COSADE, 2015)

Improving Non-profiled Attacks on Exponentiations Based on Clustering and Extracting Leakage from Multi-channel High-Resolution EM Measurements. - Robert Specht; Johann Heyszl; Martin Kleinsteuber; Georg Sigl (COSADE, 2015)

A Petite and Power Saving Design for the AES S-Box. - Markus Stefan Wamser; Lukas Holzbaur; Georg Sigl (DSD, 2015)

Low-Area Reed Decoding in a Generalized Concatenated Code Construction for PUFs. - Matthias Hiller; Ludwig Kurzinger; Georg Sigl; Sven Müelich; Sven Puchinger; Martin Bossert (ISVLSI, 2015)

Aging effects on ring-oscillator-based physical unclonable functions on FPGAs. - Stefan Gehrer; Sebastien Leger; Georg Sigl (ReConFig, 2015)

Using the reconfigurability of modern FPGAs for highly efficient PUF-based key generation. - Stefan Gehrer; Georg Sigl (ReCoSoC, 2015)

On Error Correction for Physical Unclonable Functions. - Sven Puchinger; Sven Müelich; Martin Bossert; Matthias Hiller; Georg Sigl (CoRR, 2015)

Fehlerkorrekturverfahren zur sicheren Schlüsselerzeugung mit Physical Unclonable Functions. - Matthias Hiller; Michael Pehl; Georg Sigl (Datenschutz und Datensicherheit, 2015)

Closing the gap between speed and configurability of multi-bit fault emulation environments for security and safety-critical designs. - Ralph Nyberg; Johann Heyszl; Dirk Rabe; Georg Sigl (Microprocess. Microsystems, 2015)

Squeezing Polynomial Masking in Tower Fields - A Higher-Order Masked AES S-Box. - Fabrizio De Santis; Tobias Bauer; Georg Sigl (CARDIS, 2016)

Automated Detection of Instruction Cache Leaks in Modular Exponentiation Software. - Andreas Zankl; Johann Heyszl; Georg Sigl (CARDIS, 2016)

Online Reliability Testing for PUF Key Derivation. - Matthias Hiller; Aysun Gurur Önalan; Georg Sigl; Martin Bossert (TrustED@CCS, 2016)

Hiding Higher-Order Univariate Leakages by Shuffling Polynomial Masking Schemes: A More Efficient, Shuffled, and Higher-Order Masked AES S-box. - Fabrizio De Santis; Tobias Bauer; Georg Sigl (TIS@CCS, 2016)

Practical evaluation of code injection in encrypted firmware updates. - Oscar M. Guillen; Dawin Schmidt; Georg Sigl (DATE, 2016)

Fast and Reliable PUF Response Evaluation from Unsettled Bistable Rings. - Robert Hesselbarth; Georg Sigl (DSD, 2016)

X25519 Hardware Implementation for Low-Latency Applications. - Philipp Koppermann; Fabrizio De Santis; Johann Heyszl; Georg Sigl (DSD, 2016)

Towards Efficient Evaluation of a Time-Driven Cache Attack on Modern Processors. - Andreas Zankl; Katja Miller; Johann Heyszl; Georg Sigl (ESORICS (2), 2016)

Attack on a DFA Protected AES by Simultaneous Laser Fault Injections. - Bodo Selmke; Johann Heyszl; Georg Sigl (FDTC, 2016)

Towards Side-Channel Secure Firmware Updates - A Minimalist Anomaly Detection Approach. - Oscar M. Guillen; Fabrizio De Santis; Ralf Brederlow; Georg Sigl (FPS, 2016)

Enhancing Fault Emulation of Transient Faults by Separating Combinational and Sequential Fault Propagation. - Ralph Nyberg; Johann Heyszl; Dietmar Heinz; Georg Sigl (ACM Great Lakes Symposium on VLSI, 2016)

Practical Aspects of Quantization and Tamper-Sensitivity for Physically Obfuscated Keys. - Vincent Immler; Maxim Hennig; Ludwig Kürzinger; Georg Sigl (CS2@HiPEAC, 2016)

An area-optimized serial implementation of ICEPOLE authenticated encryption schemes. - Michael Tempelmeier; Fabrizio De Santis; Jens-Peter Kaps; Georg Sigl (HOST, 2016)

MaskVer: a tool helping designers detect flawed masking implementations. - Michael Tempelmeier; Georg Sigl (IVSW, 2016)

Towards risk aware NoCs for data protection in MPSoCs. - Johanna Sepúlveda; Daniel Florez; Ramon Fernandes; César A. M. Marcon; Guy Gogniat; Georg Sigl (ReCoSoC, 2016)

A security aware routing approach for NoC-based MPSoCs. - Ramon Fernandes; César A. M. Marcon; Rodrigo Cataldo; Jarbas Silveira; Georg Sigl; Martha Johanna Sepúlveda (SBCCI, 2016)

Side channel attack on NoC-based MPSoCs are practical: NoC Prime+Probe attack. - Cezar Reinbrecht; Altamiro Amadeu Susin; Lilian Bossuet; Georg Sigl; Martha Johanna Sepúlveda (SBCCI, 2016)

A flexible framework for mobile device forensics based on cold boot attacks. - Manuel Huber 001; Benjamin Taubmann; Sascha Wessel; Hans P. Reiser; Georg Sigl (EURASIP J. Inf. Secur., 2016)

Algebraic Security Analysis of Key Generation with Physical Unclonable Functions. - Matthias Hiller; Michael Pehl; Gerhard Kramer; Georg Sigl (IACR Cryptol. ePrint Arch., 2016)

Area-Efficient PUF-Based Key Generation on System-on-Chips with FPGAs. - Stefan Gehrer; Georg Sigl (J. Circuits Syst. Comput., 2016)

Cherry-Picking Reliable PUF Bits With Differential Sequence Coding. - Matthias Hiller; Meng-Day (Mandel) Yu; Georg Sigl (IEEE Trans. Inf. Forensics Secur., 2016)

EM Side-Channel Analysis of BCH-based Error Correction for PUF-based Key Generation. - Lars Tebelmann; Michael Pehl; Georg Sigl (ASHES@CCS, 2017)

Towards post-quantum security for IoT endpoints with NTRU. - Oscar M. Guillen; Thomas Pöppelmann; Jose Maria Bermudo Mera; Elena Fuentes Bongenaar; Georg Sigl; Johanna Sepúlveda (DATE, 2017)

Compromising FPGA SoCs using malicious hardware blocks. - Nisha Jacob; Carsten Rolfes; Andreas Zankl; Johann Heyszl; Georg Sigl (DATE, 2017)

ChaCha20-Poly1305 authenticated encryption for high-speed embedded IoT applications. - Fabrizio De Santis; Andreas Schauer; Georg Sigl (DATE, 2017)

Take a moment and have some t: Hypothesis testing on raw PUF data. - Vincent Immler; Matthias Hiller; Johannes Obermaier; Georg Sigl (HOST, 2017)

Automatic generation of high-performance modular multipliers for arbitrary mersenne primes on FPGAs. - Philipp Koppermann; Fabrizio De Santis; Johann Heyszl; Georg Sigl (HOST, 2017)

Towards Protected MPSoC Communication for Information Protection against a Malicious NoC. - Johanna Sepúlveda; Andreas Zankl; Daniel Flórez; Georg Sigl (ICCS, 2017)

Exploiting Bus Communication to Improve Cache Attacks on Systems-on-Chips. - Johanna Sepúlveda; Mathieu Gross; Andreas Zankl; Georg Sigl (ISVLSI, 2017)

Towards trace-driven cache attacks on Systems-on-Chips - exploiting bus communication. - Johanna Sepúlveda; Mathieu Gross; Andreas Zankl; Georg Sigl (ReCoSoC, 2017)

A security-aware routing implementation for dynamic data protection in zone-based MPSoC. - Johanna Sepúlveda; Ramon Fernandes; César A. M. Marcon; Daniel Florez; Georg Sigl (SBCCI, 2017)

Securing FPGA SoC configurations independent of their manufacturers. - Nisha Jacob; Jakob Wittmann; Johann Heyszl; Robert Hesselbarth; Florian Wilde; Michael Pehl; Georg Sigl; Kai Fischer (SoCC, 2017)

Pushing the limits further: Sub-atomic AES. - Markus Stefan Wamser; Georg Sigl (VLSI-SoC, 2017)

How to Break Secure Boot on FPGA SoCs through Malicious Hardware. - Nisha Jacob; Johann Heyszl; Andreas Zankl; Carsten Rolfes; Georg Sigl (IACR Cryptol. ePrint Arch., 2017)

Fast and reliable PUF response evaluation from unsettled bistable rings. - Robert Hesselbarth; Johann Heyszl; Georg Sigl (Microprocess. Microsystems, 2017)

Low-latency X25519 hardware implementation: breaking the 100 microseconds barrier. - Philipp Koppermann; Fabrizio De Santis; Johann Heyszl; Georg Sigl (Microprocess. Microsystems, 2017)

Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection. - Cezar Reinbrecht; Altamiro Amadeu Susin; Lilian Bossuet; Georg Sigl; Johanna Sepúlveda (Microprocess. Microsystems, 2017)

Efficient security zones implementation through hierarchical group key management at NoC-based MPSoCs. - Martha Johanna Sepúlveda; Daniel Flórez; Vincent Immler; Guy Gogniat; Georg Sigl (Microprocess. Microsystems, 2017)

A measurement system for capacitive PUF-based security enclosures. - Johannes Obermaier; Vincent Immler; Matthias Hiller; Georg Sigl (DAC, 2018)

Where Technology Meets Security: Key Storage and Data Separation for System-on-Chips. - Georg Sigl; Mathieu Gross; Michael Pehl (ESSCIRC, 2018)

Towards the formal verification of security properties of a Network-on-Chip router. - Johanna Sepúlveda; Damian Aboul-Hassan; Georg Sigl; Bernd Becker 001; Matthias Sauer 002 (ETS, 2018)

Locked out by Latch-up? An Empirical Study on Laser Fault Injection into Arm Cortex-M Processors. - Bodo Selmke; Kilian Zinnecker; Philipp Koppermann; Katja Miller; Johann Heyszl; Georg Sigl (FDTC, 2018)

B-TREPID: Batteryless tamper-resistant envelope with a PUF and integrity detection. - Vincent Immler; Johannes Obermaier; Martin König; Matthias Hiller; Georg Sigl (HOST, 2018)

Dividing the threshold: Multi-probe localized EM analysis on threshold implementations. - Robert Specht; Vincent Immler; Florian Unterstein; Johann Heyszl; Georg Sigl (HOST, 2018)

The CAESAR-API in the real world - Towards a fair evaluation of hardware CAESAR candidates. - Michael Tempelmeier; Fabrizio De Santis; Georg Sigl; Jens-Peter Kaps (HOST, 2018)

DATA - Differential Address Trace Analysis. - Samuel Weiser; Andreas Zankl; Raphael Spreitzer; Katja Miller; Stefan Mangard; Georg Sigl (Krypto-Tag, 2018)

An embedded key management system for PUF-based security enclosures. - Johannes Obermaier; Florian Hauschild; Matthias Hiller; Georg Sigl (MECO, 2018)

Experimental Power and Performance Evaluation of CAESAR Hardware Finalists. - Michael Tempelmeier; Georg Sigl; Jens-Peter Kaps (ReConFig, 2018)

DATA - Differential Address Trace Analysis: Finding Address-based Side-Channels in Binaries. - Samuel Weiser; Andreas Zankl; Raphael Spreitzer; Katja Miller; Stefan Mangard; Georg Sigl (USENIX Security Symposium, 2018)

18 Seconds to Key Exchange: Limitations of Supersingular Isogeny Diffie-Hellman on Embedded Devices. - Philipp Koppermann; Eduard Pop; Johann Heyszl; Georg Sigl (IACR Cryptol. ePrint Arch., 2018)

High-Resolution EM Attacks Against Leakage-Resilient PRFs Explained - And An Improved Construction. - Florian Unterstein; Johann Heyszl; Fabrizio De Santis; Robert Specht; Georg Sigl (IACR Cryptol. ePrint Arch., 2018)

Fast FPGA Implementations of Diffie-Hellman on the Kummer Surface of a Genus-2 Curve. - Philipp Koppermann; Fabrizio De Santis; Johann Heyszl; Georg Sigl (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018)

The Low Area Probing Detector as a Countermeasure Against Invasive Attacks. - Michael Weiner 004; Salvador Manich; Rosa Rodríguez-Montañés; Georg Sigl (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Breaking TrustZone Memory Isolation through Malicious Hardware on a Modern FPGA-SoC. - Mathieu Gross; Nisha Jacob; Andreas Zankl; Georg Sigl (ASHES@CCS, 2019)

EyeSec: A Retrofittable Augmented Reality Tool for Troubleshooting Wireless Sensor Networks in the Field. - Martin Striegel; Carsten Rolfes; Johann Heyszl; Fabian Helfert; Maximilian Hornung; Georg Sigl (EWSN, 2019)

Improving on State Register Identification in Sequential Hardware Reverse Engineering. - Michaela Brunner; Johanna Baehr 001; Georg Sigl (HOST, 2019)

Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CAESAR Finalists. - Michael Tempelmeier; Maximilian Werner; Georg Sigl (HOST, 2019)

A Secure Dual-MCU Architecture for Robust Communication of IIoT Devices. - Matthias Niedermaier; Dominik Merli; Georg Sigl (MECO, 2019)

Efficient Intrusion Detection on Low-Performance Industrial IoT Edge Node Devices. - Matthias Niedermaier; Martin Striegel; Felix Sauer; Dominik Merli; Georg Sigl (CoRR, 2019)

Network Scanning and Mapping for IIoT Edge Node Device Security. - Matthias Niedermaier; Florian Fischer; Dominik Merli; Georg Sigl (CoRR, 2019)

Secure Physical Enclosures from Covers with Tamper-Resistance. - Vincent Immler; Johannes Obermaier; Kuan Kuan Ng; Fei Xiang Ke; JinYu Lee; Yak Peng Lim; Wei Koon Oh; Keng Hoong Wee; Georg Sigl (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019)

A Calibratable Detector for Invasive Attacks. - Michael Weiner 004; Wolfgang Wieser; Emili Lupon; Georg Sigl; Salvador Manich (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Timing Resilience for Efficient and Secure Circuits. - Grace Li Zhang; Michaela Brunner; Bing Li 005; Georg Sigl; Ulf Schlichtmann (ASP-DAC, 2020)

Extending the RISC-V Instruction Set for Hardware Acceleration of the Post-Quantum Scheme LAC. - Tim Fritzmann; Georg Sigl; Johanna Sepúlveda (DATE, 2020)

Protecting RESTful IoT Devices from Battery Exhaustion DoS Attacks. - Stefan Hristozov; Manuel Huber 001; Georg Sigl (HOST, 2020)

Efficient Hardware/Software Co-Design for Post-Quantum Crypto Algorithm SIKE on ARM and RISC-V based Microcontrollers. - Debapriya Basu Roy; Tim Fritzmann; Georg Sigl (ICCAD, 2020)

Logic Locking Induced Fault Attacks. - Michaela Brunner; Michael Gruber; Michael Tempelmeier; Georg Sigl (ISVLSI, 2020)

Secure and user-friendly over-the-air firmware distribution in a portable faraday cage. - Martin Striegel; Johann Heyszl; Florian Jakobsmeier; Yacov Matveev; Georg Sigl (WISEC, 2020)

TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix). - Grace Li Zhang; Bing Li 005; Meng Li 004; Bei Yu 001; David Z. Pan; Michaela Brunner; Georg Sigl; Ulf Schlichtmann (CoRR, 2020)

A Power Side-Channel Attack on the CCA2-Secure HQC KEM. - Thomas Schamberger; Julian Renner; Georg Sigl; Antonia Wachter-Zeh (IACR Cryptol. ePrint Arch., 2020)

Machine learning and structural characteristics for reverse engineering. - Johanna Baehr 001; Alessandro Bernardini; Georg Sigl; Ulf Schlichtmann (Integr., 2020)

Review of error correction for PUFs and evaluation on state-of-the-art FPGAs. - Matthias Hiller; Ludwig Kürzinger; Georg Sigl (J. Cryptogr. Eng., 2020)

TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing. - Grace Li Zhang; Bing Li 005; Meng Li 004; Bei Yu 001; David Z. Pan; Michaela Brunner; Georg Sigl; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography. - Tim Fritzmann; Georg Sigl; Johanna Sepúlveda (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020)

Tapeout of a RISC-V crypto chip with hardware trojans: a case-study on trojan design and pre-silicon detectability. - Alexander Hepp; Georg Sigl (CF, 2021)

The Cost of OSCORE and EDHOC for Constrained Devices. - Stefan Hristozov; Manuel Huber 001; Lei Xu; Jaro Fietz; Marco Liess; Georg Sigl (CODASPY, 2021)

Algebraic Fault Analysis of Subterranean 2.0. - Michael Gruber; Patrick Karl; Georg Sigl (FDTC, 2021)

Beyond Cache Attacks: Exploiting the Bus-based Communication Structure for Powerful On-Chip Microarchitectural Attacks. - Johanna Sepúlveda; Mathieu Gross; Andreas Zankl; Georg Sigl (ACM Trans. Embed. Comput. Syst., 2021)

DOMREP-An Orthogonal Countermeasure for Arbitrary Order Side-Channel and Fault Attack Protection. - Michael Gruber; Matthias Probst; Patrick Karl; Thomas Schamberger; Lars Tebelmann; Michael Tempelmeier; Georg Sigl (IEEE Trans. Inf. Forensics Secur., 2021)

Finding the Needle in the Haystack: Metrics for Best Trace Selection in Unsupervised Side-Channel Attacks on Blinded RSA. - Alexander Kulow; Thomas Schamberger; Lars Tebelmann; Georg Sigl (IEEE Trans. Inf. Forensics Secur., 2021)

A Second Look at the ASCAD Databases. - Maximilian Egger; Thomas Schamberger; Lars Tebelmann; Florian Lippert; Georg Sigl (COSADE, 2022)

Counteract Side-Channel Analysis of Neural Networks by Shuffling. - Manuel Brosch; Matthias Probst; Georg Sigl (DATE, 2022)

Golden Model-Free Hardware Trojan Detection by Classification of Netlist Module Graphs. - Alexander Hepp; Johanna Baehr 001; Georg Sigl (DATE, 2022)

Hardware Accelerated FrodoKEM on RISC-V. - Patrick Karl; Tim Fritzmann; Georg Sigl (DDECS, 2022)

Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis. - Johanna Baehr 001; Alexander Hepp; Michaela Brunner; Maja Malenko; Georg Sigl (DSD, 2022)

A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts. - Alexander Hepp; Tiago D. Perez; Samuel Pagliarini; Georg Sigl (ICCAD, 2022)

TOFU - Toggle Count Analysis made simple. - Michael Gruber; Georg Sigl (IACR Cryptol. ePrint Arch., 2022)

A Power Side-Channel Attack on the Reed-Muller Reed-Solomon Version of the HQC Cryptosystem. - Thomas Schamberger; Lukas Holzbaur; Julian Renner; Antonia Wachter-Zeh; Georg Sigl (IACR Cryptol. ePrint Arch., 2022)

Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoC. - Mathieu Gross; Nisha Jacob; Andreas Zankl; Georg Sigl (J. Cryptogr. Eng., 2022)

Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography. - Tim Fritzmann; Michiel Van Beirendonck; Debapriya Basu Roy; Patrick Karl; Thomas Schamberger; Ingrid Verbauwhede; Georg Sigl (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

On the application of Two-Photon Absorption for Laser Fault Injection attacks Pushing the physical boundaries for Laser-based Fault Injection. - Bodo Selmke; Maximilian Pollanka; Andreas Duensing; Emanuele Strieder; Hayden Wen; Michael Mittermair; Reinhard Kienberger; Georg Sigl (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

Toward a Human-Readable State Machine Extraction. - Michaela Brunner; Alexander Hepp; Johanna Baehr 001; Georg Sigl (ACM Trans. Design Autom. Electr. Syst., 2022)

Enhancing the Security of FPGA-SoCs via the Usage of ARM TrustZone and a Hybrid-TPM. - Mathieu Gross; Konrad Hohentanner; Stefan Wiehler; Georg Sigl (ACM Trans. Reconfigurable Technol. Syst., 2022)

ROPAD: Enhancing the Digital Ring Oscillator Probing Attempt Detector for Protecting Irregular Data Buses. - Seyed Hamidreza Moghadas; Michael Pehl; Georg Sigl (IEEE Trans. Very Large Scale Integr. Syst., 2022)

FPGANeedle: Precise Remote Fault Attacks from FPGA to CPU. - Mathieu Gross; Jonas Krautter; Dennis Gnad; Michael Gruber; Georg Sigl; Mehdi B. Tahoori (ASP-DAC, 2023)

Counterfeit Detection by Semiconductor Process Technology Inspection. - Matthias Ludwig 005; Ann-Christin Bette; Bernhard Lippmann; Georg Sigl (ETS, 2023)

CPU to FPGA Power Covert Channel in FPGA-SoCs. - Mathieu Gross; Robert Kunzelmann; Georg Sigl (IACR Cryptol. ePrint Arch., 2023)

The Impact of Hash Primitives and Communication Overhead for Hardware-Accelerated SPHINCS+. - Patrick Karl; Jonas Schupp; Georg Sigl (IACR Cryptol. ePrint Arch., 2023)

A Lightweight Firmware Resilience Engine for IoT Devices Leveraging Minimal Processor Features. - Utku Budak; Fabrizio De Santis; Georg Sigl (CSR, 2024)

ScanCamouflage: Obfuscating Scan Chains with Camouflaged Sequential and Logic Gates. - Tarik Ibrahimpasic; Grace Li Zhang; Michaela Brunner; Georg Sigl; Bing Li 005; Ulf Schlichtmann (DATE, 2024)

EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge. - Patrick Schmidt; Iuliia Topko; Matthias Stammler; Tanja Harbaum; Jürgen Becker 001; Rico Berner; Omar Ahmed; Jakub Jagielski; Thomas Seidler; Markus Abel; Marius Kreutzer; Maximilian Kirschner; et al. (DATE, 2024)

Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track. - Michaela Brunner; Hye-Hyun Lee; Alexander Hepp; Johanna Baehr 001; Georg Sigl (DDECS, 2024)

Fault-Simulation-Based Flip-Flop Classification for Reverse Engineering. - Michael Mildner; Michaela Brunner; Michael Gruber; Johanna Baehr 001; Georg Sigl (DDECS, 2024)

Switch-Glitch : Location of Fault Injection Sweet Spots by Electro-Magnetic Emanation. - Matthias Probst; Michael Gruber; Manuel Brosch; Tim Music; Georg Sigl (FDTC, 2024)

DOMREP II. - Matthias Probst; Manuel Brosch; Michael Gruber; Georg Sigl (HOST, 2024)

RISC-V Triplet: Tapeouts for Security Applications. - Jonas Schupp; Patrick Karl; Jens Nöpel; Alexander Hepp; Tim Music; Georg Sigl (NorCAS, 2024)

A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic. - Manuel Brosch; Matthias Probst; Matthias Glaser; Georg Sigl (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Post-Quantum Signatures on RISC-V with Hardware Acceleration. - Patrick Karl; Jonas Schupp; Tim Fritzmann; Georg Sigl (ACM Trans. Embed. Comput. Syst., 2024)

Uniform instruction set extensions for multiplications in contemporary and post-quantum cryptography. - Felix Oberhansl; Tim Fritzmann; Thomas Pöppelmann; Debapriya Basu Roy; Georg Sigl (J. Cryptogr. Eng., 2024)

A Cyber-Resilient DICE Architecture for Resource-Constrained Devices. - Utku Budak; Malek Safieh; Fabrizio De Santis; Georg Sigl (ARES (EU Projects Symposium Workshops 1), 2025)

A Lightweight Firmware Resilience Engine for Real-Time Operating Systems. - Utku Budak; Fabrizio De Santis; Osman Yasar; Malek Safieh; Georg Sigl (CSR, 2025)

Multi-Partner Project: Open-Source Design Tools for Co-Development of AI Algorithms and AI Chips: (Initial Stage). - Mehdi B. Tahoori; Jürgen Becker 001; Jörg Henkel; Wolfgang Kunz; Ulf Schlichtmann; Georg Sigl; Jürgen Teich; Norbert Wehn (DATE, 2025)

High-Performance FPGA Accelerator for the Post-quantum Signature Scheme CROSS. - Patrick Karl; Francesco Antognazza; Alessandro Barenghi; Gerardo Pelosi; Georg Sigl (IACR Cryptol. ePrint Arch., 2025)

ProbeNav - Fast, precise and repeatable positioning of electromagnetic probes for local Side-Channel Attacks. - Matthias Probst; Alexander Wiesent; Michael Gruber; Georg Sigl (IACR Cryptol. ePrint Arch., 2025)

A Horizontal Attack on the Codes and Restricted Objects Signature Scheme (CROSS). - Jonas Schupp; Georg Sigl (IACR Cryptol. ePrint Arch., 2025)

Side-Channel Analysis of Integrate-and-Fire Neurons Within Spiking Neural Networks. - Matthias Probst; Manuel Brosch; Georg Sigl (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)