Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core. - Harris E. Michail; Athanasios P. Kakarountas; Athanasios Milidonis; George A. Panagiotakopoulos; Vasilis N. Thanasoulis; Costas E. Goutis (ICECS, 2006)

Server side hashing core exceeding 3 Gbps of throughput. - Harris E. Michail; George A. Panagiotakopoulos; Vasilis N. Thanasoulis; Athanasios Kakarountas; Costas E. Goutis (Int. J. Secur. Networks, 2007)

Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse. - Athanasios Milidonis; Vasileios Porpodas; Nikolaos Alachiotis 002; Athanasios P. Kakarountas; Harris E. Michail; George A. Panagiotakopoulos; Costas E. Goutis (IET Comput. Digit. Tech., 2009)

Decoupled Processors Architecture for Accelerating Data Intensive Applications using Scratch-Pad Memory Hierarchy. - Athanasios Milidonis; Nikolaos Alachiotis 002; Vasileios Porpodas; Harris E. Michail; George A. Panagiotakopoulos; Athanasios P. Kakarountas; Costas E. Goutis (J. Signal Process. Syst., 2010)