A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS. - Harish Krishnamurthy; Vaibhav A. Vaidya; Pavan Kumar 001; George E. Matthew; Sheldon Weng; Bharani Thiruvengadam; Wayne Proefrock; Krishnan Ravichandran; Vivek De (VLSIC, 2014)

A 0.4V∼1V 0.2A/mm2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS. - Pavan Kumar 001; Vaibhav A. Vaidya; Harish Krishnamurthy; Stephen T. Kim; George E. Matthew; Sheldon Weng; Bharani Thiruvengadam; Wayne Proefrock; Krishnan Ravichandran; Vivek De (CICC, 2015)

20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS. - Harish Kumar Krishnamurthy; Vaibhav A. Vaidya; Sheldon Weng; Krishnan Ravichandran; Pavan Kumar 001; Stephen T. Kim; Rinkle Jain; George E. Matthew; Jim Tschanz; Vivek De (ISSCC, 2017)

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. - Pascal Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (ISSCC, 2018)

A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS. - Harish Kumar Krishnamurthy; Vaibhav A. Vaidya; Pavan Kumar 001; Rinkle Jain; Sheldon Weng; Stephen T. Kim; George E. Matthew; Nachiket V. Desai; Xiaosen Liu; Krishnan Ravichandran; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2018)

A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS. - Harish Kumar Krishnamurthy; Sheldon Weng; George E. Matthew; Nachiket V. Desai; Ruchir Saraswat; Krishnan Ravichandran; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2018)

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{ text{MIN}}$ Optimization. - Pascal Andreas Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (IEEE J. Solid State Circuits, 2019)