An attribute grammar approach to high-level automated hardware synthesis. - George Economakos; George K. Papakonstantinou; Panayotis Tsanakas (Inf. Softw. Technol., 1995)

Hardware compilation using attribute grammars. - George Economakos; George K. Papakonstantinou; Kiamal Z. Pekmestzi; Panayotis Tsanakas (CHARME, 1997)

Automatic Hardware Synthesis of Nested Loops Using UET Grids and VHDL. - Nectarios Koziris; Theodore Andronikos; George Economakos; George K. Papakonstantinou; Panayotis Tsanakas (HPCN Europe, 1997)

AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems. - George Economakos; George K. Papakonstantinou; Panayotis Tsanakas (DATE, 1998)

Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis Environment. - George Economakos; George K. Papakonstantinou (EUROMICRO, 1998)

Behavioral synthesis of digital filters using attribute grammars. - George Economakos; George K. Papakonstantinou; Panayiotis Tsanakas (EUSIPCO, 1998)

Incorporating multi-pass attribute grammars for the high-level synthesis of ASICs. - George Economakos; George K. Papakonstantinou; Panayotis Tsanakas (SAC, 1998)

Refinement and Property Checking in High-Level Synthesis using Attribute Grammars. - George Economakos; George K. Papakonstantinou (CHARME, 1999)

Language Based Design Verification with Semantic Analysis. - George Economakos; George K. Papakonstantinou (EUROMICRO, 1999)

A formal method for hardware design using attribute grammars. - George Economakos; George K. Papakonstantinou (ICECS, 1999)

A complete specification and implementation methodology for high-level hardware transformations. - George Economakos; Ioannis Drositis; George K. Papakonstantinou (ICECS, 2000)

A top-down interactive behavioral synthesis environment. - Ioannis Poulakis; Petros Economakos; George Economakos; Ioannis Panagopoulos; George K. Papakonstantinou (ICECS, 2000)

Behavioral synthesis with systemC. - George Economakos; Petros Oikonomakos; Ioannis Panagopoulos; Ioannis Poulakis; George K. Papakonstantinou (DATE, 2001)

A Multi-Lingual Synthesis and Verification Environment. - George Economakos; Stergios Stergiou; George K. Papakonstantinou; Vassilios Zoukos (DSD, 2001)

Handling advanced scheduling heuristics under a hardware compiler generation environment. - George Economakos; Petros Oikonomakos; Ioannis Poulakis; George K. Papakonstantinou; Stamatis Georgoulis (Knowl. Based Syst., 2002)

Lowpower design of multipliers using a full-adder isolation technique. - Konstantinos Anagnostopoulos; George Economakos (ICECS, 2005)

A Methodology for Design Space Exploration in Embedded DSP Applications. - George Economakos; Kostas Anagnostopoulos; Isidoros Sideris (ICECS, 2006)

High-level synthesis with reconfigurable datapath components. - George Economakos (IPDPS, 2006)

Behavioral synthesis with SystemC and PSL assertions for interface specification. - George Economakos (ISCAS, 2006)

Bit level architectural exploration technique for the design of low power multipliers. - George Economakos; Kostas Anagnostopoulos (ISCAS, 2006)

A cache based stack folding technique for high performance Java processors. - Isidoros Sideris; George Economakos; Kiamal Z. Pekmestzi (JTRES, 2006)

A Reconfigurable Arithmetic Data-path Based On Regular Interconnection. - Sotirios Xydis; George Economakos; Kiamal Z. Pekmestzi (AHS, 2007)

High-level synthesis heuristics for run-time reconfigurable architectures. - George Economakos; Sotirios Xydis (EUSIPCO, 2007)

Building embedded DSP applications in a Java modeling framework. - Isidoros Sideris; Dimitris Pilitsos; George Economakos; Kiamal Z. Pekmestzi (EUSIPCO, 2007)

A regular interconnection scheme for efficient mapping of DSP kernels into reconfigurable hardware. - Sotirios Xydis; George Economakos; Kiamal Z. Pekmestzi (EUSIPCO, 2007)

Power-Efficient and Low Latency Implementation of Programmable FIR filters Using Carry-Save Arithmetic. - Dimitris Bekiaris; Isidoros Sideris; George Economakos; Kiamal Z. Pekmestzi (ICECS, 2007)

Run-time reconfigurable solutions for adaptive control applications. - George Economakos; Christoforos E. Economakos; Sotirios Xydis (ICINCO-SPSMC, 2007)

Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme. - Sotirios Xydis; George Economakos; Kiamal Z. Pekmestzi (ICSAMOS, 2007)

Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility. - Sotirios Xydis; George Economakos; Dimitrios Soudris; Kiamal Z. Pekmestzi (AHS, 2008)

Efficient implementation of biomedical hardware using open source descriptions and behavioral synthesis. - George Economakos (BIBE, 2008)

A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis. - George Economakos; Sotirios Xydis (DSD, 2008)

Optimized FPGA implementations of demanding PLC programs based on hardware high-level synthesis. - Christoforos E. Economakos; George Economakos (ETFA, 2008)

Efficient serial and parallel implementation of programmable fir filters based on the merging technique. - Dimitris Bekiaris; George Economakos; Kiamal Z. Pekmestzi (EUSIPCO, 2008)

A flexible architecture for DSP applications combining high performance arithmetic with small scale configurability. - Sotirios Xydis; Isidoros Sideris; George Economakos; Kiamal Z. Pekmestzi (EUSIPCO, 2008)

An instruction set extension for java bytecodes translation acceleration. - Isidoros Sideris; Kiamal Z. Pekmestzi; George Economakos (ICSAMOS, 2008)

A predecoding technique for ILP exploitation in Java processors. - Isidoros Sideris; Kiamal Z. Pekmestzi; George Economakos (J. Syst. Archit., 2008)

Flexible Datapath Synthesis through Arithmetically Optimized Operation Chaining. - Sotirios Xydis; Ioannis Triantafyllou; George Economakos; Kiamal Z. Pekmestzi (AHS, 2009)

Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis. - George Economakos; Sotirios Xydis (DSD, 2009)

Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology. - George Kiokes; George Economakos; Angelos Amditis; Nikolaos K. Uzunoglu (DSD, 2009)

Architectural exploration in biomedical hardware design using a novel behavioral synthesis methodology. - George Economakos (EUSIPCO, 2009)

Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations. - Kostas Siozios; Dimitrios Soudris; George Economakos (DPS, 2009)

A design methodology for high-performance and low-leakage fixed-point transpose FIR filters. - Dimitris Bekiaris; Sotirios Xydis; George Economakos; Kiamal Z. Pekmestzi (ICECS, 2009)

High-level synthesis with coarse grain reconfigurable components. - George Economakos; Sotirios Xydis (IPDPS, 2009)

Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths. - Sotirios Xydis; George Economakos; Kiamal Z. Pekmestzi (Integr., 2009)

Extending an embedded RISC microprocessor for efficient translation based Java execution. - Isidoros Sideris; Kiamal Z. Pekmestzi; George Economakos (Microprocess. Microsystems, 2009)

Construction of dual mode components for reconfiguration aware high-level synthesis. - George Economakos; Sotirios Xydis; Ioannis Koutras; Dimitrios Soudris (DATE, 2010)

BIT-width exploration over 3D architectures using high-level synthesis. - Ioannis Koutras; Antonis Papanikolaou; George Economakos; Dimitrios Soudris (ICECS, 2010)

Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology. - Sotirios Xydis; Christos Skouroumounis; Kiamal Z. Pekmestzi; Dimitrios Soudris; George Economakos (ISCAS, 2010)

Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures. - Iasonas Filippopoulos; Iraklis Anagnostopoulos; Alexandros Bartzas; Dimitrios Soudris; George Economakos (ISVLSI, 2010)

High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures. - Sotirios Xydis; Kiamal Z. Pekmestzi; Dimitrios Soudris; George Economakos (ISVLSI, 2010)

A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning. - Sotirios Xydis; Kiamal Z. Pekmestzi; Dimitrios Soudris; George Economakos (ISVLSI (Selected papers), 2010)

Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching. - Sotirios Xydis; Christos Skouroumounis; Kiamal Z. Pekmestzi; Dimitrios Soudris; George Economakos (ISVLSI, 2010)

A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework. - Dimitris Bekiaris; Antonis Papanikolaou; Christos Papameletis; Dimitrios Soudris; George Economakos; Kiamal Z. Pekmestzi (PATMOS, 2010)

Design and experimentation with low-power morphable multipliers. - Efstathios Sotiriou-Xanthopoulos; Dionysios Diamantopoulos; George Economakos; Dimitrios Soudris (ICECS, 2011)

Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow. - Dimitris Bekiaris; George Economakos; Efstathios Sotiriou-Xanthopoulos; Dimitrios Soudris (ReConFig, 2011)

High Performance and Area Efficient Flexible DSP Datapath Synthesis. - Sotirios Xydis; George Economakos; Dimitrios Soudris; Kiamal Z. Pekmestzi (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Power Optimization Opportunities for a Reconfigurable Arithmetic Component in the Deep Submicron Domain. - Dimitris Bekiaris; George Economakos (DSD, 2012)

A Methodology for Efficient Use of OpenCL, ESL and FPGAs in Multi-core Architectures. - Alexandros Bartzas; George Economakos (Euro-Par Workshops, 2012)

ESL as a Gateway from OpenCL to FPGAs: Basic Ideas and Methodology Evaluation. - George Economakos (Panhellenic Conference on Informatics, 2012)

Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments. - Dimitris Bekiaris; Efstathios Sotiriou-Xanthopoulos; George Economakos; Dimitrios Soudris (ReCoSoC, 2012)

Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs. - Sotirios Xydis; Kiamal Z. Pekmestzi; Dimitrios Soudris; George Economakos (ACM Trans. Design Autom. Electr. Syst., 2012)

Efficient C level hardware design for floating point biomedical DSP applications. - Harry Sidiropoulos; Efthymia Kazakou; Christoforos E. Economakos; George Economakos (BIBE, 2013)

Rapid prototyping of digital controllers using FPGAs and ESL/HLS design methodologies. - Christoforos E. Economakos; Harry Sidiropoulos; George Economakos (ICAC, 2013)

HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips. - Dionysios Diamantopoulos; Kostas Siozios; Efstathios Sotiriou-Xanthopoulos; George Economakos; Dimitrios Soudris (IPDPS Workshops, 2013)

A new design paradigm for floating point DSP applications based on ESL/HLS and FPGAs? - Dionysios Diamantopoulos; Christoforos E. Economakos; Dimitrios Soudris; George Economakos (ISSPIT, 2013)

A Process-based Reconfigurable SystemC Module for simulation speedup. - Efstathios Sotiriou-Xanthopoulos; Kostas Siozios; George Economakos; Dimitrios Soudris (ICSAMOS, 2013)

Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks. - Efstathios Sotiriou-Xanthopoulos; Sotirios Xydis; Kostas Siozios; George Economakos; Dimitrios Soudris (PARMA-DITAM@HiPEAC, 2014)

Using high-level synthesis to build memory and datapath optimized DSP accelerators. - Dionysios Diamantopoulos; George Economakos; Dionysios I. Reisis (ICECS, 2014)

Program-based and Model-based PLC Design Environment for Multicore FPGA Architectures. - Christoforos E. Economakos; Michael G. Skarpetis; George Economakos (ICINCO (1), 2014)

A scalable FPGA-based architecture for digital controllers and a corresponding rapid prototyping design methodology. - Christoforos E. Economakos; Maria P. Tzamtzi; George Economakos (ISIE, 2014)

Hardware accelerated rician denoise algorithm for high performance magnetic resonance imaging. - Efstathios Sotiriou-Xanthopoulos; Sotirios Xydis; Kostas Siozios; George Economakos; Dimitrios Soudris (MobiHealth, 2014)

Co-design of many-accelerator heterogeneous systems exploiting virtual platforms. - Efstathios Sotiriou-Xanthopoulos; Sotirios Xydis; Kostas Siozios; George Economakos (ICSAMOS, 2014)

Systematic Design and Evaluation of Reconfigurable Arithmetic Components in the Deep submicron Domain. - Dimitris Bekiaris; Sotirios Xydis; George Economakos (J. Circuits Syst. Comput., 2014)

A framework for rapid evaluation of heterogeneous 3-D NoC architectures. - Efstathios Sotiriou-Xanthopoulos; Dionysios Diamantopoulos; Kostas Siozios; George Economakos; Dimitrios Soudris (Microprocess. Microsystems, 2014)

Plug&Chip: A Framework for Supporting Rapid Prototyping of 3D Hybrid Virtual SoCs. - Dionysios Diamantopoulos; Efstathios Sotiriou-Xanthopoulos; Kostas Siozios; George Economakos; Dimitrios Soudris (ACM Trans. Embed. Comput. Syst., 2014)

Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures. - Efstathios Sotiriou-Xanthopoulos; Dionysios Diamantopoulos; George Economakos (ARC, 2015)

Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems. - Efstathios Sotiriou-Xanthopoulos; Sotirios Xydis; Kostas Siozios; George Economakos; Dimitrios Soudris (FPL, 2015)

Performance improvements in a modern hardware design environment for control applications. - Christoforos E. Economakos; Maria P. Tzamtzi; Michael G. Skarpetis; George Economakos (ICIT, 2015)

Using advanced FPGA SoC technologies for the design of industrial control applications. - Christoforos E. Economakos; George Kiokes; George Economakos (IISA, 2015)

Comparison of OpenCL based design for a medical device on heterogeneous architectures with CPU, GPU and FPGA. - Efthymia Kazakou; George Economakos (Panhellenic Conference on Informatics, 2015)

A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models. - Efstathios Sotiriou-Xanthopoulos; Shalina Percy Delicia; Peter Figuli; Kostas Siozios; George Economakos; Jürgen Becker 001 (SAMOS, 2015)

A virtual platform for exploring hierarchical interconnection for many-accelerator systems. - Efstathios Sotiriou-Xanthopoulos; Sotirios Xydis; Kostas Siozios; George Economakos (SAMOS, 2015)

An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures. - Efstathios Sotiriou-Xanthopoulos; Leonard Masing; Kostas Siozios; George Economakos; Dimitrios Soudris; Jürgen Becker 001 (SAMOS, 2016)

An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems. - Efstathios Sotiriou-Xanthopoulos; Sotirios Xydis; Kostas Siozios; George Economakos; Dimitrios Soudris (ACM Trans. Embed. Comput. Syst., 2016)

A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis. - Efstathios Sotiriou-Xanthopoulos; Sotirios Xydis; Kostas Siozios; George Economakos; Dimitrios Soudris (ACM Trans. Embed. Comput. Syst., 2016)