ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks. - Haoxing Ren; George F. Kokai; Walker J. Turner; Ting-Sheng Ku (DAC, 2020)

Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization. - Mingjie Liu; Walker J. Turner; George F. Kokai; Brucek Khailany; David Z. Pan; Haoxing Ren (DATE, 2021)

TAG: Learning Circuit Spatial Embedding from Layouts. - Keren Zhu 001; Hao Chen 059; Walker J. Turner; George F. Kokai; Po-Hsuan Wei; David Z. Pan; Haoxing Ren (ICCAD, 2022)

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies. - Hao Chen 059; Walker J. Turner; Sanquan Song; Keren Zhu 001; George F. Kokai; Brian Zimmer; C. Thomas Gray; Brucek Khailany; David Z. Pan; Haoxing Ren (ISPD, 2022)