Towards Accurate Performance Modeling of RISC-V Designs. - Odysseas Chatzopoulos; George-Marios Fragkoulis; George Papadimitriou 001; Dimitris Gizopoulos (CoRR, 2021)

Harpocrates: Breaking the Silence of CPU Faults through Hardware-in-the-Loop Program Generation. - Nikos Karystinos; Odysseas Chatzopoulos; George-Marios Fragkoulis; George Papadimitriou 001; Dimitris Gizopoulos; Sudhanva Gurumurthi (ISCA, 2024)

Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension. - George-Marios Fragkoulis; Nikos Karystinos; George Papadimitriou 001; Dimitris Gizopoulos (CoRR, 2024)