Approaching Ideal NoC Latency with Pre-Configured Routes. - George Michelogiannakis; Dionisios N. Pnevmatikatos; Manolis Katevenis (NOCS, 2007)

Elastic-buffer flow control for on-chip networks. - George Michelogiannakis; James D. Balfour; William J. Dally (HPCA, 2009)

Router designs for elastic buffer on-chip networks. - George Michelogiannakis; William J. Dally (SC, 2009)

Evaluating Bufferless Flow Control for On-chip Networks. - George Michelogiannakis; Daniel Sánchez 003; William J. Dally; Christos Kozyrakis (NOCS, 2010)

An analysis of on-chip interconnection networks for large-scale chip multiprocessors. - Daniel Sánchez 003; George Michelogiannakis; Christos Kozyrakis (ACM Trans. Archit. Code Optim., 2010)

Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. - George Michelogiannakis; Nan Jiang 009; Daniel Becker 003; William J. Dally (IEEE Comput. Archit. Lett., 2011)

Evaluating Elastic Buffer and Wormhole Flow Control. - George Michelogiannakis; Daniel Becker 003; William J. Dally (IEEE Trans. Computers, 2011)

Network congestion avoidance through Speculative Reservation. - Nan Jiang 009; Daniel U. Becker; George Michelogiannakis; William J. Dally (HPCA, 2012)

Adaptive Backpressure: Efficient buffer management for on-chip networks. - Daniel U. Becker; Nan Jiang 009; George Michelogiannakis; William J. Dally (ICCD, 2012)

A detailed and flexible cycle-accurate Network-on-Chip simulator. - Nan Jiang 009; Daniel U. Becker; George Michelogiannakis; James D. Balfour; Brian Towles; David E. Shaw; John Kim 001; William J. Dally (ISPASS, 2013)

Channel reservation protocol for over-subscribed channels and destinations. - George Michelogiannakis; Nan Jiang 009; Daniel Becker 003; William J. Dally (SC, 2013)

Elastic Buffer Flow Control for On-Chip Networks. - George Michelogiannakis; William J. Dally (IEEE Trans. Computers, 2013)

Collective memory transfers for multi-core chips. - George Michelogiannakis; Alexander Williams; Samuel Williams 001; John Shalf (ICS, 2014)

OpenSoC Fabric: On-Chip Network Generator: Using Chisel to Generate a Parameterizable On-Chip Interconnect Fabric. - Farzad Fatollahi-Fard; David Donofrio; George Michelogiannakis; John Shalf (NoCArc@MICRO, 2014)

Variable-width datapath for on-chip network static power reduction. - George Michelogiannakis; John Shalf (NOCS, 2014)

Extending Summation Precision for Network Reduction Operations. - George Michelogiannakis; Xiaoye S. Li; David H. Bailey; John Shalf (Int. J. Parallel Program., 2015)

OpenSoC Fabric: On-chip network generator. - Farzad Fatollahi-Fard; David Donofrio; George Michelogiannakis; John Shalf (ISPASS, 2016)

TiDA: High-Level Programming Abstractions for Data Locality Management. - Didem Unat; Tan Nguyen 001; Weiqun Zhang; Muhammed Nufail Farooqi; Burak Bastem; George Michelogiannakis; Ann S. Almgren; John Shalf (ISC, 2016)

APHiD: Hierarchical Task Placement to Enable a Tapered Fat Tree Topology for Lower Power and Cost in HPC Networks. - George Michelogiannakis; Khaled Z. Ibrahim; John Shalf; Jeremiah J. Wilke; Samuel Knight; Joseph P. Kenny (CCGrid, 2017)

Last Level Collective Hardware Prefetching For Data-Parallel Applications. - George Michelogiannakis; John Shalf (HiPC, 2017)

CASPER - Configurable design space exploration of programmable architectures for machine learning using beyond moore devices. - Dilip P. Vasudevan; George Michelogiannakis; David Donofrio; John Shalf (NANOARCH, 2017)

Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies. - Dilip P. Vasudevan; Anastasiia Butko; George Michelogiannakis; David Donofrio; John Shalf (ISC Workshops, 2017)

Architectural Opportunities and Challenges from Emerging Photonics in Future Systems. - George Michelogiannakis; Benjamin Aivazi; Yiwen Shen 002; Larry Dennison; John Shalf; Keren Bergman; Madeleine Glick (PSC, 2018)

The Pitfalls of Provisioning Exascale Networks: A Trace Replay Analysis for Understanding Communication Performance. - Joseph P. Kenny; Khachik Sargsyan; Samuel Knight; George Michelogiannakis; Jeremiah J. Wilke (ISC, 2018)

TIGER: topology-aware task assignment approach using ising machines. - Anastasiia Butko; George Michelogiannakis; David Donofrio; John Shalf (CF, 2019)

Extending classical processors to support future large scale quantum accelerators. - Anastasiia Butko; George Michelogiannakis; David Donofrio; John Shalf (CF, 2019)

SpecLock: Speculative Lock Forwarding. - Pooria M. Yaghini; George Michelogiannakis; Paul V. Gratz (ICCD, 2019)

PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments. - Dilip P. Vasudevan; George Michelogiannakis; David Donofrio; John Shalf (ISPASS, 2019)

3D photonics as enabling technology for deep 3D DRAM stacking. - Sebastian Werner 002; Pouya Fotouhi; Xian Xiao; Marjan Fariborz; S. J. Ben Yoo; George Michelogiannakis; Dilip P. Vasudevan (MEMSYS, 2019)

Bandwidth steering in HPC using silicon nanophotonics. - George Michelogiannakis; Yiwen Shen 002; Min Yee Teh; Xiang Meng 003; Benjamin Aivazi; Taylor L. Groves; John Shalf; Madeleine Glick; Manya Ghobadi; Larry Dennison; Keren Bergman (SC, 2019)

A Computational Temporal Logic for Superconducting Accelerators. - Georgios Tzimpragos; Dilip Vasudevan; Nestan Tsiskaridze; George Michelogiannakis; Advait Madhavan; Jennifer Volk; John Shalf; Timothy Sherwood (ASPLOS, 2020)

Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization. - Anastasiia Butko; George Michelogiannakis; Samuel Williams 001; Costin Iancu; David Donofrio; John Shalf; Jonathan Carter 002; Irfan Siddiqi (ICRC, 2020)

TAGO: rethinking routing design in high performance reconfigurable networks. - Min Yee Teh; Yu-Han Hung; George Michelogiannakis; Shijia Yan; Madeleine Glick; John Shalf; Keren Bergman (SC, 2020)

TIGER: Topology-aware Assignment using Ising machines Application to Classical Algorithm Tasks and Quantum Circuit Gates. - Anastasiia Butko; Ilyas Turimbetov; George Michelogiannakis; David Donofrio; Didem Unat; John Shalf (CoRR, 2020)

Language Support for Navigating Architecture Design in Closed Form. - Weilong Cui; Georgios Tzimpragos; Yu Tao; Joseph McMahan; Deeksha Dangwal; Nestan Tsiskaridze; George Michelogiannakis; Dilip P. Vasudevan; Timothy Sherwood (ACM J. Emerg. Technol. Comput. Syst., 2020)

PINE: Photonic Integrated Networked Energy efficient datacenters (ENLITENED Program) [Invited]. - Madeleine Glick; Nathan C. Abrams; Qixiang Cheng; Min Yee Teh; Yu-Han Hung; Oscar A. Jimenez; Songtao Liu; Yoshitomo Okawachi; Xiang Meng 003; Leif Johansson; Manya Ghobadi; Larry Dennison; et al. (JOCN, 2020)

SRNoC: A Statically-Scheduled Circuit-Switched Superconducting Race Logic NoC. - George Michelogiannakis; Darren Lyles; Patricia Gonzalez-Guerrero; Meriam Gay Bautista; Dilip Vasudevan; Anastasiia Butko (IPDPS, 2021)

Superconducting Shuttle-flux Shift Buffer for Race Logic. - Meriam Gay Bautista; Patricia Gonzalez-Guerrero; Darren Lyles; George Michelogiannakis (MWSCAS, 2021)

Temporal Computing With Superconductors. - Georgios Tzimpragos; Jennifer Volk; Dilip Vasudevan; Nestan Tsiskaridze; George Michelogiannakis; Advait Madhavan; John Shalf; Timothy Sherwood (IEEE Micro, 2021)

Temporal and SFQ pulse-streams encoding for area-efficient superconducting accelerators. - Patricia Gonzalez-Guerrero; Meriam Gay Bautista; Darren Lyles; George Michelogiannakis (ASPLOS, 2022)

Superconducting Digital DIT Butterfly Unit for Fast Fourier Transform Using Race Logic. - Meriam Gay Bautista; Patricia Gonzalez-Guerrero; Darren Lyles; Kylie Huch; George Michelogiannakis (NEWCAS, 2022)

Establishing Cooperative Computation with Hardware Embassies. - Alvin Oliver Glova; Yukai Yang; Yiyao Wan; Zhizhou Zhang 002; George Michelogiannakis; Jonathan Balkind; Timothy Sherwood (SEED, 2022)

PaST-NoC: A Packet-Switched Superconducting Temporal NoC. - Darren Lyles; Patricia Gonzalez-Guerrero; Meriam Gay Bautista; George Michelogiannakis (CoRR, 2022)

A Case For Intra-rack Resource Disaggregation in HPC. - George Michelogiannakis; Benjamin Klenk; Brandon Cook 001; Min Yee Teh; Madeleine Glick; Larry Dennison; Keren Bergman; John Shalf (ACM Trans. Archit. Code Optim., 2022)

Efficient Intra-Rack Resource Disaggregation for HPC Using Co-Packaged DWDM Photonics. - George Michelogiannakis; Yehia Arafa; Brandon Cook 001; Liang Yuan Dai; Abdel-Hameed A. Badawy; Madeleine Glick; Yuyang Wang 003; Keren Bergman; John Shalf (CLUSTER, 2023)

Reliable Hyperdimensional Reasoning on Unreliable Emerging Technologies. - Hamza Errahmouni Barkam; Sanggeon Yun; Hanning Chen; Paul Gensler; Albi Mema; Andrew Ding; George Michelogiannakis; Hussam Amrouch; Mohsen Imani (ICCAD, 2023)

An Area Efficient Superconducting Unary CNN Accelerator. - Patricia Gonzalez-Guerrero; Kylie Huch; Nirmalendu Patra; Doru-Thom Popovici; George Michelogiannakis (ISQED, 2023)

MC-ELMM: Multi-Chip Endurance-Limited Memory Management. - Andrew M. Bartolo; Mohamed M. Sabry Aly; George Michelogiannakis; Subhasish Mitra (MEMSYS, 2023)

Analyzing Resource Utilization in an HPC System: A Case Study of NERSC's Perlmutter. - Jie Li 057; George Michelogiannakis; Brandon Cook 001; Dulanya Cooray; Yong Chen 001 (ISC, 2023)

Analyzing Resource Utilization in an HPC System: A Case Study of NERSC Perlmutter. - Jie Li 057; George Michelogiannakis; Brandon Cook 001; Dulanya Cooray; Yong Chen 001 (CoRR, 2023)

Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications. - Meriam Gay Bautista; Patricia Gonzalez-Guerrero; Darren Lyles; George Michelogiannakis (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Job Scheduling in High Performance Computing Systems with Disaggregated Memory Resources. - Jie Li 057; George Michelogiannakis; Samuel Maloney; Brandon Cook 001; Estela Suarez; John Shalf; Yong Chen 001 (CLUSTER, 2024)

Scheduling and Allocation of Disaggregated Memory Resources in HPC Systems. - Jie Li 057; George Michelogiannakis; Brandon Cook 001; John Shalf; Yong Chen 001 (IPDPS (Workshops), 2024)

Area Efficient Asynchronous SFQ Pulse Round-Robin Distribution Network. - Meriam Gay Bautista; Darren Lyles; Kylie Huch; Patricia Gonzalez-Guerrero; George Michelogiannakis (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Toward Practical Superconducting Accelerators for Machine Learning Using U-SFQ. - Patricia Gonzalez-Guerrero; Kylie Huch; Nirmalendu Patra; Doru-Thom Popovici; George Michelogiannakis (ACM J. Emerg. Technol. Comput. Syst., 2024)

Enabling Classical-Quantum Interface Using Digital SFQ for Pulse-Phase Driven Control for Superconducting Qubits. - Meriam Gay Bautista-Jurney; Patricia Gonzalez-Guerrero; George Michelogiannakis; Anastasiia Butko (ISCAS, 2025)