FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability. - George Kalokerinos; Vassilis Papaefstathiou; George Nikiforos; Stamatis G. Kavadias; Manolis Katevenis; Dionisios N. Pnevmatikatos; Xiaojun Yang (ICSAMOS, 2009)

Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface. - Christoforos Kachris; George Nikiforos; Stamatis G. Kavadias; Vassilis Papaefstathiou; Manolis Katevenis (ReConFig, 2010)

Fine-grain OpenMP runtime support with explicit communication hardware primitives. - Pranav Tendulkar; Vassilis Papaefstathiou; George Nikiforos; Stamatis G. Kavadias; Dimitrios S. Nikolopoulos; Manolis Katevenis (DATE, 2011)

NP-SARC: Scalable network processing in the SARC multi-core FPGA platform. - Christoforos Kachris; George Nikiforos; Vassilis Papaefstathiou; Stamatis G. Kavadias; Manolis Katevenis (J. Syst. Archit., 2013)

Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability. - George Kalokerinos; Vassilis Papaefstathiou; George Nikiforos; Stamatis G. Kavadias; Xiaojun Yang; Dionisios N. Pnevmatikatos; Manolis Katevenis (Trans. High Perform. Embed. Archit. Compil., 2019)