An ECL RISC microprocessor designed for two level cache. - David Roberts; Tim Layman; George Taylor (Compcon, 1990)

The TLB Slice - A Low-Cost High-Speed Address Translation Mechanism. - George Taylor; Peter Davies; Michael Farmwald (ISCA, 1990)

A 533-MHz BiCMOS superscalar RISC microprocessor. - Cliff A. Maier; James A. Markevitch; Cheryl Senter Brashears; Tim Sippel; Earl T. Cohen; Jim Blomgren; James G. Ballard; Jay Pattin; Viki Moldenhauer; Jeffrey A. Thomas; George Taylor (IEEE J. Solid State Circuits, 1997)

Data Integration Issues for a Farm Decision Support System. - Marion Jones; George Taylor (Trans. GIS, 2004)