Low-power design of array architectures. - Dimitrios Soudris; George Theodoridis; S. Theoharis; Adonios Thanailakis (ICECS, 1996)

A novel approach for reducing the switching activity in two-level logic circuits. - George Theodoridis; S. Theoharis; Dimitrios Soudris; Odysseas G. Koufopavlou; Costas E. Goutis (ICECS, 1996)

An efficient probabilistic method for logic circuits using real delay gate model. - George Theodoridis; S. Theoharis; Dimitrios Soudris; Thanos Stouraitis; Constantinos E. Goutis (ISCAS (1), 1999)

A New Method for Low Power Design of Two-Level Logic Circuits. - George Theodoridis; Spyros Theoharis; Dimitrios Soudris; Constantinos E. Goutis (VLSI Design, 1999)

Low power design of a multi-mode transceiver. - Dimitrios Soudris; Minas Perakis; Haris Mizas; Vasilios A. Mardiris; Kosfas Katis; Chrissavgi Dre; A. E. Tzimas; E. G. Metaxakis; Grigorios Kalivas; Nikolaos D. Zervas; Spyros Theoharis; George Theodoridis; et al. (ISCAS, 2000)

Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions. - George Theodoridis; S. Theoharis; Nikolaos D. Zervas; Constantinos E. Goutis (PATMOS, 2000)

Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers. - Nikolaos D. Zervas; S. Theoharis; Athanasios Kakarountas; George Theodoridis; Dimitrios Soudris; Constantinos E. Goutis (PATMOS, 2000)

A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model. - George Theodoridis; Spyros Theoharis; Dimitrios Soudris; Constantinos E. Goutis (VLSI Design, 2001)

A Fast and Accurate Method of Power Estimation for Logic Level Networks. - George Theodoridis; S. Theoharis; Dimitrios Soudris; Constantinos E. Goutis (VLSI Design, 2001)

A fast and accurate delay dependent method for switching estimation of large combinational circuits. - S. Theoharis; George Theodoridis; Dimitrios Soudris; Constantinos E. Goutis; Adonios Thanailakis (J. Syst. Archit., 2002)

Power aware data type refinement on the HIPERLAN/2. - Gregory Dimitroulakos; Athanasios Milidonis; Michalis D. Galanis; George Theodoridis; Costas E. Goutis; Francky Catthoor (ICECS, 2003)

A novel high-speed counter with counting rate independent of the counter's length. - Athanasios P. Kakarountas; George Theodoridis; Kyriakos S. Papadomanolakis; Costas E. Goutis (ICECS, 2003)

An reconfigurable multiplier in GF(2m) for elliptic curve cryptosystem. - Paris Kitsos; George Theodoridis; Odysseas G. Koufopavlou (ICECS, 2003)

An efficient reconfigurable multiplier architecture for Galois field GF(2m). - Paris Kitsos; George Theodoridis; Odysseas G. Koufopavlou (Microelectron. J., 2003)

A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. - Michalis D. Galanis; Athanasios Milidonis; George Theodoridis; Dimitrios Soudris; Constantinos E. Goutis (DATE, 2004)

Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Constantinos E. Goutis (FCCM, 2004)

A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Constantinos E. Goutis (FPGA, 2004)

Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Constantinos E. Goutis (FPL, 2004)

A high performance data-path to accelerate DSP kernels. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Costas E. Goutis (ICECS, 2004)

Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Constantinos E. Goutis (PATMOS, 2004)

A Novel Constant-Time Fault-Secure Binary Counter. - Dimitris Karatasos; Athanasios Kakarountas; George Theodoridis; Constantinos E. Goutis (PATMOS, 2004)

A Novel Data-Path for Accelerating DSP Kernels. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Dimitrios Soudris; Costas E. Goutis (SAMOS, 2004)

An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications. - Athanasios Milidonis; Grigoris Dimitroulakos; Michalis D. Galanis; George Theodoridis; Constantinos E. Goutis; Francky Catthoor (SCOPES, 2004)

A Framework for Data Partitioning for C++ Data-Intensive Applications. - Athanasios Milidonis; Gregory Dimitroulakos; Michalis D. Galanis; Athanasios P. Kakarountas; George Theodoridis; Constantinos E. Goutis; Francky Catthoor (Des. Autom. Embed. Syst., 2004)

A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms. - Michalis D. Galanis; Athanasios Milidonis; George Theodoridis; Dimitrios Soudris; Constantinos E. Goutis (IPDPS, 2005)

A methodology for partitioning DSP applications in hybrid reconfigurable systems. - Michalis D. Galanis; Athanasios Milidonis; George Theodoridis; Dimitrios Soudris; Constantinos E. Goutis (ISCAS (2), 2005)

A method for partitioning applications in hybrid reconfigurable architectures. - Michalis D. Galanis; Athanasios Milidonis; George Theodoridis; Dimitrios Soudris; Costas E. Goutis (Des. Autom. Embed. Syst., 2005)

A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Constantinos E. Goutis (J. Circuits Syst. Comput., 2005)

Behavioral-level event-driven power management for DECT digital receivers. - Nikolaos D. Zervas; George Theodoridis; Dimitrios Soudris (Microelectron. J., 2005)

Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support. - Nikolaos Vassiliadis; George Theodoridis; Spiridon Nikolaidis 001 (ARC, 2006)

An automated development framework for a RISC processor with reconfigurable instruction set extensions. - Nikolaos Vassiliadis; George Theodoridis; Spiridon Nikolaidis 001 (IPDPS, 2006)

Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers. - Athanasios Kakarountas; Nikolaos D. Zervas; George Theodoridis; Haralambos Michail; Dimitrios Soudris (J. Low Power Electron., 2006)

A high-performance data path for synthesizing DSP kernels. - Michalis D. Galanis; George Theodoridis; Spyros Tragoudas; Constantinos E. Goutis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications. - Athanasios Kakarountas; Haralambos Michail; Athanasios Milidonis; Costas E. Goutis; George Theodoridis (J. Supercomput., 2006)

The ARISE Reconfigurable Instruction Set Extensions Framework. - Nikolaos Vassiliadis; George Theodoridis; Spiridon Nikolaidis 001 (ICSAMOS, 2007)

Automated framework for partitioning DSP applications in hybrid reconfigurable platforms. - Michalis D. Galanis; Athanasios Milidonis; George Theodoridis; Dimitrios Soudris; Constantinos E. Goutis (Microprocess. Microsystems, 2007)

ARISE Machines: Extending Processors with Hybrid Accelerators. - Nikolaos Vassiliadis; George Theodoridis; Spiridon Nikolaidis 001 (ARC, 2008)

An integer linear programming model for mapping applications on hybrid systems. - George Theodoridis; Nikolaos Vassiliadis; Spiridon Nikolaidis 001 (IET Comput. Digit. Tech., 2009)

An Application Development Framework for ARISE Reconfigurable Processors. - Nikolaos Vassiliadis; George Theodoridis; Spiridon Nikolaidis 001 (ACM Trans. Reconfigurable Technol. Syst., 2009)

The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators. - Nikolaos Vassiliadis; George Theodoridis; Spiridon Nikolaidis 001 (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A high throughput pipelined architecture for H.264/AVC deblocking filter. - Nikolaos Kefalas; George Theodoridis (ICECS, 2010)

High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach. - George Athanasiou; Chara I. Chalkou; D. Bardis; Harris E. Michail; George Theodoridis; Costas E. Goutis (SECRYPT, 2012)

On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function. - Harris E. Michail; George Athanasiou; Andreas Gregoriades; George Theodoridis; Costas E. Goutis (SECRYPT, 2012)

On the exploitation of a high-throughput SHA-256 FPGA design for HMAC. - Harris E. Michail; George Athanasiou; Vasilios I. Kelefouras; George Theodoridis; Costas E. Goutis (ACM Trans. Reconfigurable Technol. Syst., 2012)

High-performance FPGA implementations of the cryptographic hash function JH. - George Athanasiou; Harris E. Michail; George Theodoridis; Costas E. Goutis (IET Comput. Digit. Tech., 2013)

A Systematic Flow for Developing Totally Self-Checking Architectures for SHA-1 and SHA-2 Cryptographic Hash Families. - George Athanasiou; George Theodoridis; Costas E. Goutis; Harris E. Michail; Takis Kasparis (J. Circuits Syst. Comput., 2013)

A Hybrid ILP-CP Model for Mapping Directed Acyclic Task Graphs to Multicore Architectures. - Andreas Emeretlis; George Theodoridis; Panayiotis Alefragis; Nikolaos S. Voros (IPDPS Workshops, 2014)

An 8K-UHD capable 8-stage pipeline deblocking filter for H.264/AVC. - Nikolaos Kefalas; George Theodoridis (ISCCSP, 2014)

FPGA Implementations for Volterra DFEs. - Andreas Emeretlis; George Theodoridis (Panhellenic Conference on Informatics, 2014)

High-performance FPGA implementations of volterra DFEs for optical fiber systems. - Andreas Emeretlis; George Theodoridis; George-Othon Glentis (ReConFig, 2014)

Optimising the SHA-512 cryptographic hash function on FPGAs. - Georgios Athanasiou; Harris E. Michail; George Theodoridis; Costas E. Goutis (IET Comput. Digit. Tech., 2014)

On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs. - Harris E. Michail; Georgios Athanasiou; George Theodoridis; Costas E. Goutis (Integr., 2014)

FPGA implementation of a MIMO DFE IN 40 GB/S DQPSK optical links. - Andreas Emeretlis; V. Kefelouras; George Theodoridis; Maki Nanou; Christina Tanya Politi; Kristina Georgoulakis; George-Othon Glentis (EUSIPCO, 2015)

A parallel luma-chroma filtering architecture for H.264/AVC deblocking filter. - Nikolaos Kefalas; George Theodoridis (ICCE-Berlin, 2015)

40 Gb/s FPGA implementation of a reduced complexity volterra DFE for DQPSK optical links. - Maki Nanou; Andreas Emeretlis; Christina Tanya Politi; George Theodoridis; Kristina Georgoulakis; George-Othon Glentis (ICTON, 2015)

Mapping DAGs on Heterogeneous Platforms Using Logic-Based Benders Decompostion. - Andreas Emeretlis; George Theodoridis; Panayiotis Alefragis; Nikos S. Voros (ISVLSI, 2015)

A high performance 5 stage pipeline architecture for the H.264/AVC deblocking filter. - Nikolaos Kefalas; George Theodoridis (Integr., 2015)

A hybrid approach for mapping and scheduling on heterogeneous multicore systems. - Andreas Emeretlis; George Theodoridis; Panayiotis Alefragis; Nikolaos S. Voros (SAMOS, 2016)

Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs. - Harris E. Michail; George Athanasiou; Vasilios I. Kelefouras; George Theodoridis; Thanos Stouraitis; Costas E. Goutis (J. Circuits Syst. Comput., 2016)

Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions' architectures. - Harris E. Michail; Georgios Athanasiou; George Theodoridis; Andreas Gregoriades; Costas E. Goutis (Microprocess. Microsystems, 2016)

A Logic-Based Benders Decomposition Approach for Mapping Applications on Heterogeneous Multicore Platforms. - Andreas Emeretlis; George Theodoridis; Panayiotis Alefragis; Nikolaos S. Voros (ACM Trans. Embed. Comput. Syst., 2016)

High-throughput FPGA implementation of the CCSDS 122.0-B-1 compression standard. - Nikolaos Kefalas; George Theodoridis (PATMOS, 2017)

Task graph mapping and scheduling on heterogeneous architectures under communication constraints. - Andreas Emeretlis; T. Tsakoulis; George Theodoridis; Panayiotis Alefragis; Nikos S. Voros (SAMOS, 2017)

Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach. - Panayiotis Alefragis; George Theodoridis; Merkourios Katsimpris; Christos Valouxis; Christos Gogos; George Goulas; Nikolaos S. Voros; Simon Reder; Koray Kasnakli; Marcus Bednara; David Müller 005; Umut Durak; et al. (ARC, 2018)

A High Performance Bitplane Encoder for the CCSDS 122.0-B-1 Compression Standard. - Nikolaos Kefalas; George Theodoridis (TSP, 2018)

Static Mapping of Applications on Heterogeneous Multi-Core Platforms Combining Logic-Based Benders Decomposition with Integer Linear Programming. - Andreas Emeretlis; George Theodoridis; Panayiotis Alefragis; Nikos S. Voros (ACM Trans. Design Autom. Electr. Syst., 2018)

Implementing VESA Display Stream Compression Encoder in FPGAs. - Nikolaos Kefalas; George Theodoridis (PATMOS, 2019)

Low-memory and high-performance architectures for the CCSDS 122.0-B-1 compression standard. - Nikolaos Kefalas; George Theodoridis (Integr., 2019)

Exploring the FPGA Implementations of the LBlock, Piccolo, Twine, and Klein Ciphers. - S. Moraitis; D. Seitanidis; George Theodoridis; Odysseas G. Koufopavlou (VLSI-SOC, 2020)

A Multi-stage Hybrid Approach for Mapping Applications on Heterogeneous Multi-core Platforms. - Andreas Emeretlis; George Theodoridis; Panayiotis Alefragis; Nikos S. Voros (VLSI-SoC, 2022)

An FPGA implementation of the VESA Display Stream Compression decoder. - Nikolaos Kefalas; George Theodoridis (VLSI-SoC, 2022)

Evaluating Versal ACAP and conventional FPGA platforms for AI inference. - Aimilios Leftheriotis; Aphrodite Tzomaka; Dimitrios Danopoulos; George Lentaris; George Theodoridis; Dimitrios Soudris (MOCAST, 2023)

Multi-Partner Project: Secure Hardware Accelerated Data Analytics for 6G Networks: The PRIVATEER Approach. - Ilias Papalamprou; Aimilios Leftheriotis; Apostolis Garos; Georgios Gardikis; Maria Christopoulou; George Xilouris; Lampros Argyriou; Antonia Karamatskou; Nikolaos Papadakis; Emmanouil Kalotychos; Nikolaos Chatzivasileiadis; Dimosthenis Masouros; et al. (DATE, 2025)