Assertion Based Design of Timed Finite State Machine. - Alexander Shkil; Anatolii Miroshnyk; Georgiy Kulak; Kyrylo Pshenychnyi (EWDTS, 2021)

In-Memory Fault as Address Simulation. - Wajeb Gharibi; Svetlana Chumachenko; Maryna Miroshnyk; Marina Abashidze; Eugenia Litvinova; Georgiy Kulak; Vladimir Hahanov; Alexander Mishchenko (EWDTS, 2023)