In-line metrology and inspection for process control during 3D stacking of IC's. - Sandip Halder; Ingrid De Wolf; Alain Phommahaxay; Andy Miller; Mireille Maenhoudt; Gerald Beyer; Bart Swinnen; Eric Beyne (3DIC, 2011)

3D stacking using Cu-Cu direct bonding. - Y. H. Hu; C. S. Liu; M. J. Lii; Kenneth J. Rebibis; Anne Jourdain; Antonio La Manna; Gerald Beyer; Eric Beyne; C. H. Yu (3DIC, 2011)

Analysis of microbump induced stress effects in 3D stacked IC technologies. - Andrej Ivankovic; Geert Van der Plas; V. Moroz; M. Choi; Vladimir Cherman; Abdelkarim Mercha; Paul Marchal; Marcel Gonzalez; Geert Eneman; Wenqi Zhang; Thibault Buisson; Mikael Detalle; et al. (3DIC, 2011)

Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding. - Alain Phommahaxay; Anne Jourdain; Greet Verbinnen; Tobias Woitke; Peter Bisson; Markus Gabriel; Walter Spiess; Alice Guerrero; Jeremy McCutcheon; Rama Puligadda; Pieter Bex; Axel Van den Eede; et al. (3DIC, 2011)

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps. - Wei Guo; Geert Van der Plas; Andrej Ivankovic; Geert Eneman; Vladimir Cherman; Bart De Wachter; Abdelkarim Mercha; Mario Gonzalez; Yann Civale; Augusto Redolfi; Thibault Buisson; A. Jourdan; et al. (ICICDT, 2012)

Reliability challenges for barrier/liner system in high aspect ratio through silicon vias. - Yunlong Li; Stefaan Van Huylenbroeck; Els Van Besien; Xiaoping Shi; Chen Wu; Michele Stucchi; Gerald Beyer; Eric Beyne; Ingrid De Wolf; Kristof Croes (Microelectron. Reliab., 2014)

Permanent wafer bonding in the low temperature by using various plasma enhanced chemical vapour deposition dielectrics. - Soon-Wook Kim; Lan Peng; Andy Miller; Gerald Beyer; Eric Beyne; Chung-Sun Lee (3DIC, 2015)

Die to wafer 3D stacking for below 10um pitch microbumps. - Jaber Derakhshandeh; Lin Hou; Inge De Preter; Carine Gerets; Samuel Suhard; Vikas Dubey; Geraldine Jamieson; Fumihiro Inoue; Tomas Webers; Pieter Bex; Giovanni Capuz; Eric Beyne; et al. (3DIC, 2016)

Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module. - Stefaan Van Huylenbroeck; Yunlong Li; Michele Stucchi; Lieve Bogaerts; Joeri De Vos; Gerald Beyer; Eric Beyne; Mohand Brouri; Praveen Nalla; Sanjay Gopinath; Matthew Thorum; Joe Richardson; et al. (3DIC, 2016)

Extreme wafer thinning optimization for via-last applications. - Anne Jourdain; Joeri De Vos; Fumihiro Inoue; Kenneth J. Rebibis; Andy Miller; Gerald Beyer; Eric Beyne; Edward Walsby; Jash Patel; Oliver Ansell; Janet Hopkins; Huma Ashraf; et al. (3DIC, 2016)

High-density and low-leakage novel embedded 3D MIM capacitor on Si interposer. - C. Roda Neve; Mikael Detalle; Philip Nolmans; Yunlong Li; Joeri De Vos; Geert Van der Plas; Gerald Beyer; Eric Beyne (3DIC, 2016)

TSV process-induced MOS reliability degradation. - Yunlong Li; Michele Stucchi; Stefaan Van Huylenbroeck; Geert Van der Plas; Gerald Beyer; Eric Beyne; Kristof Croes (IRPS, 2018)

Process Complexity and Cost Considerations of Multi-Layer Die Stacks. - Dimitrios Velenis; Joeri De Vos; Soon-Wook Kim; Jaber Derakhshandeh; Pieter Bex; Giovanni Capuz; Samuel Suhard; Kenneth June Rebibis; Stefaan Van Huylenbroeck; Erik Jan Marinissen; Alain Phommahaxay; Andy Miller; et al. (3DIC, 2019)

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. - Anabela Veloso; Anne Jourdain; D. Radisic; Rongmei Chen; G. Arutchelvan; B. O'Sullivan; Hiroaki Arimura; Michele Stucchi; An De Keersgieter; M. Hosseini; T. Hopf; K. D'Have; et al. (VLSI Technology and Circuits, 2022)

Nano-Through Silicon Vias (nTSV) for Backside Power Delivery Networks (BSPDN). - Eric Beyne; Anne Jourdain; Gerald Beyer (VLSI Technology and Circuits, 2023)

Clean Dicing: An Alternative Blade Dicing Technique for Minimising Particles in 3D Heterogeneous Integration. - Akito Hiro; Damien Jon Leech; Geert Schoofs; John Slabbekoorn; Alain Phommahaxay; Koen Kennes; Gerald Beyer; Eric Beyne (3DIC, 2024)

Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias. - P. Zhao; Liesbeth Witters; Anne Jourdain; Michele Stucchi; Nicolas Jourdan 002; J. W. Maes; H. Bana; C. Zhu; R. Chukka; F. Sebaai; Kevin Vandersmissen; N. Heylen; et al. (VLSI Technology and Circuits, 2024)