Package induced stress impact on transistor performance for ultra-thin SoC. - Md. Enamul Kabir; Dave Young; Bahattin Kilic; Ioan Sauciuc; Carl Sapp; Gerald S. Leatherman (IRPS, 2015)

Reliability of dual-damascene local interconnects featuring cobalt on 10 nm logic technology. - F. Griggio; James Palmer 002; F. Pan; N. Toledo; Anthony Schmitz; Ilan Tsameret; R. Kasim; Gerald S. Leatherman; Jeffery Hicks; A. Madhavan; J. Shin; J. Steigerwald; et al. (IRPS, 2018)

Reliability studies of a 10nm high-performance and low-power CMOS technology featuring 3rd generation FinFET and 5th generation HK/MG. - Anisur Rahman; Javier Dacuña; Pinakpani Nayak; Gerald S. Leatherman; Stephen Ramey (IRPS, 2018)

A Reliability Overview of Intel's 10+ Logic Technology. - Rohit Grover; Tony Acosta; C. AnDyke; Emre Armagan; C. Auth; Sunny Chugh; K. Downes; M. Hattendorf; N. Jack; S. Joshi; R. Kasim; Gerald S. Leatherman; et al. (IRPS, 2020)