Secure Design Flow of FPGA Based RISC-V Implementation. - Ali Shuja Siddiqui; Geraldine Shirley; Shreya Bendre; Girija Bhagwat; Jim Plusquellic; Fareena Saqib (IVSW, 2019)

Multilayer Camouflaged Secure Boot for SoCs. - Ali Shuja Siddiqui; Geraldine Shirley; Sam Reji Joseph; Yutian Gui; Jim Plusquellic; Marten van Dijk; Fareena Saqib (MTV, 2019)

A Survey and Analysis on SoC Platform Security in ARM, Intel and RISC-V Architecture. - Geraldine Shirley Nicholas; Yutian Gui; Fareena Saqib (MWSCAS, 2020)

Hardware Secure Execution and Simulation Model Correlation using IFT on RISC-V. - Geraldine Shirley Nicholas; Bhavin Thakar; Fareena Saqib (ACM Great Lakes Symposium on VLSI, 2021)

A Lightweight Delay-based Authentication Scheme for DMA Attack Mitigation. - Yutian Gui; Ali Shuja Siddiqui; Geraldine Shirley Nicholas; Marcus Hughes; Fareena Saqib (ISQED, 2021)

A Secure Boot Framework with Multi-security Features and Logic-Locking Applications for Reconfigurable Logic. - Geraldine Shirley Nicholas; Ali Shuja Siddiqui; Sam Reji Joseph; Gregory Williams; Fareena Saqib (J. Hardw. Syst. Secur., 2021)

Dynamic Key Updates for LUT Locked Design. - Jakub Slowik; Gregory Williams; Rummah Albashir; Anthony Samagio; Geraldine Shirley Nicholas; Fareena Saqib (HOST, 2022)

Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V. - Geraldine Shirley Nicholas; Dhruvakumar Vikas Aklekar; Bhavin Thakar; Fareena Saqib (Cryptogr., 2023)

AutoDetect: Novel Autoencoding Architecture for Counterfeit IC Detection. - Chaitanya Bhure; Geraldine Shirley Nicholas; Shajib Ghosh; Navid Asadi; Fareena Saqib (J. Hardw. Syst. Secur., 2024)