A robust analog interface system for submicron CMOS video DSP. - William Redman-White; Roy Duffee; Simon Bramwell; Hans Rijns; Shirley James; James Tijou; Gerard van der Weide (IEEE J. Solid State Circuits, 1998)

Design of high-performance asynchronous sigma delta modulators with a binary quantizer with hysteresis. - Sotir Ouzounov; Engel Roza; Hans Hegt; Gerard van der Weide; Arthur H. M. van Roermund (CICC, 2004)

CMOS V-I converter with 75dB SFDR and 360μW power consumption. - Sotir Ouzounov; Engel Roza; Hans Hegt; Gerard van der Weide; Arthur H. M. van Roermund (ESSCIRC, 2004)

A low power implementation for the transmit path of a UWB transceiver. - Sudhir Aggarwal; Domine Leenaerts; Remco van de Beek; Gerard van der Weide; Harish Kundur; Jos Bergervoet; Alan L. Landesman; Yifeng Zhang 003; Charles J. Razzell; Helen Waite; Raf Roovers (CICC, 2005)

A fast-hopping single-PLL 3-band UWB synthesizer in 0.25μm SiGe BiCMOS. - Remco van de Beek; Domine Leenaerts; Gerard van der Weide (ESSCIRC, 2005)

A CMOS V-I converter with 75-dB SFDR and 360-μW power consumption. - Sotir Ouzounov; Engel Roza; Johannes A. (Hans) Hegt; Gerard van der Weide; Arthur H. M. van Roermund (IEEE J. Solid State Circuits, 2005)

An interference-robust receiver for ultra-wideband radio in SiGe BiCMOS technology. - Raf Roovers; Domine M. W. Leenaerts; Jos Bergervoet; Kundur S. Harish; Remco C. H. van de Beek; Gerard van der Weide; Helen Waite; Yifeng Zhang 003; Sudhir Aggarwal; Charles J. Razzell (IEEE J. Solid State Circuits, 2005)

A fast-hopping single-PLL 3-band MB-OFDM UWB synthesizer. - Remco van de Beek; Domine M. W. Leenaerts; Gerard van der Weide (IEEE J. Solid State Circuits, 2006)

Analysis and design of high-performance asynchronous sigma-delta Modulators with a binary quantizer. - Sotir Ouzounov; Engel Roza; Johannes A. Hegt; Gerard van der Weide; Arthur H. M. van Roermund (IEEE J. Solid State Circuits, 2006)

A WiMedia-Compliant UWB Transceiver in 65nm CMOS. - Jos Bergervoet; Harish Kundur Subramaniyan; S. Lee; Domine Leenaerts; Remco van de Beek; Gerard van der Weide; Raf Roovers (ISSCC, 2007)

A 56mW CT Quadrature Cascaded ΣΔ Modulator with 77dB DR in a Near Zero-IF 20MHz Band. - Lucien J. Breems; Robert Rutten; Robert H. M. van Veldhoven; Gerard van der Weide; Henk A. H. Termeer (ISSCC, 2007)

A Broadband Receive Chain in 65nm CMOS. - S. Lee; Jos Bergervoet; Harish Kundur Subramaniyan; Domine Leenaerts; Raf Roovers; Remco van de Beek; Gerard van der Weide (ISSCC, 2007)

Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption. - Sotir Ouzounov; Engel Roza; Hans Hegt; Gerard van der Weide; Arthur H. M. van Roermund (Integr., 2007)

A 56 mW Continuous-Time Quadrature Cascaded ΣΔ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band. - Lucien J. Breems; Robert Rutten; Robert H. M. van Veldhoven; Gerard van der Weide (IEEE J. Solid State Circuits, 2007)

A 0.6-to-10GHz Receiver Front-End in 45nm CMOS. - Remco van de Beek; Jos Bergervoet; Harish Kundur; Domine Leenaerts; Gerard van der Weide (ISSCC, 2008)

A 65nm CMOS inductorless triple-band-group WiMedia UWB PHY. - Domine Leenaerts; Remco van de Beek; Jos Bergervoet; Harish Kundur; Gerard van der Weide; Ajay Kapoor; Tian Yan Pu; Yu Fang; Yujuan Wang; Biju Joseph Mukkada; Hong Sair Lim; Madhu Kiran; et al. (ISSCC, 2009)

A 65 nm CMOS Inductorless Triple Band Group WiMedia UWB PHY. - Domine Leenaerts; Remco van de Beek; Jos Bergervoet; Harish Kundur; Gerard van der Weide; Ajay Kapoor; Tian Yan Pu; Yu Fang; Yujuan Wang; Biju Joseph Mukkada; Hong Sair Lim; Madhu Kiran; et al. (IEEE J. Solid State Circuits, 2009)

A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist. - Konstantinos Doris; Erwin Janssen; Claudio Nani; Athon Zanikopoulos; Gerard van der Weide (ISSCC, 2011)

A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS. - Kostas Doris; Erwin Janssen; Claudio Nani; Athon Zanikopoulos; Gerard van der Weide (IEEE J. Solid State Circuits, 2011)

An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals. - Yu Lin 003; Kostas Doris; Erwin Janssen; Athon Zanikopoulos; Alessandro Murroni; Gerard van der Weide; Hans Hegt; Arthur H. M. van Roermund (ESSCIRC, 2013)

An 11b 3.6GS/s time-interleaved SAR ADC in 65nm CMOS. - Erwin Janssen; Kostas Doris; Athon Zanikopoulos; Alessandro Murroni; Gerard van der Weide; Yu Lin 003; Ludo Alvado; Frederic Darthenay; Yannick Fregeais (ISSCC, 2013)