Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation. - Bernhard Hoppe; Gerd Neuendorf; Doris Schmitt-Landsiedel; J. Will Specks (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Pipelined architecture for fast CMOS buffer RAMs. - Doris Schmitt-Landsiedel; Bernhard Hoppe; Gerd Neuendorf; Maria Wurm; Josef Winnerl (IEEE J. Solid State Circuits, 1990)