Formal Verification of Descriptions with Distinct Order of Memory Operations. - Gerd Ritter; Holger Hinrichsen; Hans Eveking (ASIAN, 1999)

Formal Verification of Designs with Complex Control by Symbolic Simulation. - Gerd Ritter; Hans Eveking; Holger Hinrichsen (CHARME, 1999)

Automatic Verification of Scheduling Results in High-Level Synthesis. - Hans Eveking; Holger Hinrichsen; Gerd Ritter (DATE, 1999)

Automatische Synthese und Verifikation von RISC-Prozessoren. - Holger Hinrichsen; Gerd Ritter; Hans Eveking (MBMV, 1999)

Sequential Equivalence Checking by Symbolic Simulation. - Gerd Ritter (FMCAD, 2000)

Formale Verifikation der Register-Allokation. - Claudia Blank; Gerd Ritter; Holger Hinrichsen; Hans Eveking (MBMV, 2000)

Symbolic simulation techniques-state-of-the-art and applications. - Claudia Blank; Hans Eveking; Jens Levihn; Gerd Ritter (HLDVT, 2001)

Formal sequential equivalence checking of digital systems by symbolic simulation. - Gerd Ritter (2001)