Level Assignment for Displaying Combinational Logic. - Rolf Drechsler; Wolfgang Günther 001; Lothar Linhard; Gerhard Angst (DSD, 2001)

Efficient Automatic Visualization of SystemC Designs. - Daniel Große; Rolf Drechsler; Lothar Linhard; Gerhard Angst (FDL, 2003)

Recursive bi-partitioning of netlists for large number of partitions. - Rolf Drechsler; Wolfgang Günther 001; Thomas Eschbach; Lothar Linhard; Gerhard Angst (J. Syst. Archit., 2003)

Visualization of SystemC Designs. - Christian Genz; Rolf Drechsler; Gerhard Angst; Lothar Linhard (ISCAS, 2007)

Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. - Robert Wille; Görschwin Fey; Marc Messing; Gerhard Angst; Lothar Linhard; Rolf Drechsler (DSD, 2008)

Parallelized Critical Path Search in Electrical Circuit Designs. - Pascal Bolzhauser; Anthony Sulistio; Gerhard Angst; Christoph Reich (PDCAT, 2009)

Minimally Invasive HW/SW Co-debug Live Visualization on Architecture Level. - Pascal Pieper; Ralf Wimmer 001; Gerhard Angst; Rolf Drechsler (ACM Great Lakes Symposium on VLSI, 2021)

The Scale4Edge RISC-V Ecosystem. - Wolfgang Ecker; Peer Adelt; Wolfgang Müller 003; Reinhold Heckmann; Milos Krstic; Vladimir Herdt; Rolf Drechsler; Gerhard Angst; Ralf Wimmer 001; Andreas Mauderer; Rafael Stahl; Karsten Emrich; et al. (DATE, 2022)