Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms. - Carlos Flores Fajardo; Zhen Fang 002; Ravi R. Iyer 001; German Fabila Garcia; Seung Eun Lee; Li Zhao 002 (DAC, 2011)

Cost-effectively offering private buffers in SoCs and CMPs. - Zhen Fang 002; Li Zhao 002; Ravishankar R. Iyer 001; Carlos Flores Fajardo; German Fabila Garcia; Seung Eun Lee; Bin Li 018; Steve R. King; Xiaowei Jiang; Srihari Makineni (ICS, 2011)

Design of a low power SoC testchip for wearables and IoTs. - May Wu; Ravi Iyer 001; Yatin Hoskote; Steven Zhang; Julio Zamora-Esquivel; German Fabila Garcia; Ilya Klotchkov; Mukesh Bhartiya (Hot Chips Symposium, 2015)

Actor-Oriented Design Patterns for Performance Modeling of Wireless Communications in Cyber-physical Systems. - Rafael Rosales; Wael Guibène; German Fabila Garcia (Q2SWinet@MSWiM, 2018)