The Intel IA-64 Compiler Code Generator. - Jay Bharadwaj; William Y. Chen; Weihaw Chuang; Gerolf Hoflehner; Kishore N. Menezes; Kalyan Muthukumar; Jim Pierce (IEEE Micro, 2000)

Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. - R. David Weldon; Steven S. Chang; Hong Wang 003; Gerolf Hoflehner; Perry H. Wang; Daniel M. Lavery; John Paul Shen (Interaction between Compilers and Computer Architectures, 2002)

Post-Pass Binary Adaptation for Software-Based Speculative Precomputation. - Shih-Wei Liao; Perry H. Wang; Hong Wang 003; John Paul Shen; Gerolf Hoflehner; Daniel M. Lavery (PLDI, 2002)

Optimization for the Intel® Itanium ®Architectur Register Stack. - Alex Settle; Daniel A. Connors; Gerolf Hoflehner; Daniel M. Lavery (CGO, 2003)

The compiler as a validation and evaluation tool. - Gerolf Hoflehner; Daniel M. Lavery; David C. Sehr (COCV@ETAPS, 2003)

Compiler Optimizations for Transaction Processing Workloads on Itanium® Linux Systems. - Gerolf Hoflehner; Knud Kirkegaard; Rod Skinner; Daniel M. Lavery; Yong-Fong Lee; Wei Li 015 (MICRO, 2004)

Comparative characterization of SPEC CPU2000 and CPU2006 on Itanium architecture. - Arun Kejariwal; Gerolf Hoflehner; Darshan Desai; Daniel M. Lavery; Alexandru Nicolau; Alexander V. Veidenbaum (SIGMETRICS, 2007)

Performance Characterization of Itanium® 2-Based Montecito Processor. - Darshan Desai; Gerolf Hoflehner; Arun Kejariwal; Daniel M. Lavery; Alexandru Nicolau; Alexander V. Veidenbaum; Cameron McNairy (SPEC Benchmark Workshop, 2009)

Strategies for Predicate-Aware Register Allocation. - Gerolf Hoflehner (CC, 2010)

AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designs. - Guilherme Ottoni; Gautham N. Chinya; Gerolf Hoflehner; Jamison D. Collins; Amit Kumar; Ethan Schuchman; David R. Ditzel; Ronak Singhal; Hong Wang 003 (Conf. Computing Frontiers, 2011)