A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O. - Dennis Michael Fischette; Alvin Leng Sun Loke; Michael M. Oshima; Bruce Andrew Doyle; Roland Bakalski; Richard Joseph DeSantis; Anand Thiruvengadam; Charles Lin Wang; Gerry R. Talbot; Emerson S. Fang (ISSCC, 2010)

An Embedded All-Digital Circuit to Measure PLL Response. - Dennis Michael Fischette; Alvin Leng Sun Loke; Richard Joseph DeSantis; Gerry R. Talbot (IEEE J. Solid State Circuits, 2010)

Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors. - Bruce Andrew Doyle; Alvin Leng Sun Loke; Sanjeev K. Maheshwari; Charles Lin Wang; Dennis Michael Fischette; Jeffrey G. Cooper; Sanjeev K. Aggarwal; Tin Tin Wee; Chad O. Lackey; Harishkumar S. Kedarnath; Michael M. Oshima; Gerry R. Talbot; et al. (A-SSCC, 2011)