On Mixed PTL/Static Logic for Low-power and High-speed Circuits. - Geun Rae Cho; Tom Chen 001 (VLSI Design, 2001)

On The Impact of Technology Scaling On Mixed PTL/Static Circuits. - Geun Rae Cho; Tom Chen 001 (ICCD, 2002)

Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. - Geun Rae Cho; Tom Chen 001 (ISQED, 2002)

On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. - Geun Rae Cho; Tom Chen 001 (IWLS, 2002)

Applications of Evolution Algorithms to the synthesis of single/Dual-rail mixed PTL/Static Logic for low-Power Applications. - Geun Rae Cho; Tom Chen 001 (SEAL, 2002)

Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. - Geun Rae Cho; Tom Chen 001 (ISQED, 2003)

On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. - Geun Rae Cho; Tom Chen 001 (VLSI Design, 2003)

Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. - Geun Rae Cho; Tom Chen 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A high supply voltage bandgap reference circuit using drain-extended MOS devices. - Geun Rae Cho; Kyung Woon Hwang; Tag Gon Kim (IEICE Electron. Express, 2013)

Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability. - Moon Gi Seok; Daejin Park; Geun Rae Cho; Tag Gon Kim (VLSI-SoC, 2014)