Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems. - Ghassem Jaberipur; Behrooz Parhami; Mohammad Ghodsi (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding. - Ghassem Jaberipur; Behrooz Parhami; Mohammad Ghodsi (J. VLSI Signal Process., 2006)

Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic. - Ghassem Jaberipur; Behrooz Parhami (IET Circuits Devices Syst., 2007)

Binary-coded decimal digit multipliers. - Ghassem Jaberipur; Amir Kaivani (IET Comput. Digit. Tech., 2007)

A Nonspeculative Maximally Redundant Signed Digit Adder. - Ghassem Jaberipur; Saeid Gorgin 001 (CSICC, 2008)

Constant-time addition with hybrid-redundant numbers: Theory and implementations. - Ghassem Jaberipur; Behrooz Parhami (Integr., 2008)

Fully Redundant Decimal Arithmetic. - Saeid Gorgin 001; Ghassem Jaberipur (IEEE Symposium on Computer Arithmetic, 2009)

Unified Approach to the Design of Modulo-(2n +/- 1) Adders Based on Signed-LSB Representation of Residues. - Ghassem Jaberipur; Behrooz Parhami (IEEE Symposium on Computer Arithmetic, 2009)

A fully redundant decimal adder and its application in parallel decimal multipliers. - Saeid Gorgin 001; Ghassem Jaberipur (Microelectron. J., 2009)

Improving the Speed of Parallel Decimal Multiplication. - Ghassem Jaberipur; Amir Kaivani (IEEE Trans. Computers, 2009)

An improved maximally redundant signed digit adder. - Ghassem Jaberipur; Saeid Gorgin 001 (Comput. Electr. Eng., 2010)

Fully redundant decimal addition and subtraction using stored-unibit encoding. - Amir Kaivani; Ghassem Jaberipur (Integr., 2010)

Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value. - Ghassem Jaberipur; Behrooz Parhami; Saeid Gorgin 001 (IEEE Trans. Computers, 2010)

On building general modular adders from standard binary arithmetic components. - Ghassem Jaberipur; Behrooz Parhami; Saeed Nejati (ACSCC, 2011)

A Family of High Radix Signed Digit Adders. - Saeid Gorgin 001; Ghassem Jaberipur (IEEE Symposium on Computer Arithmetic, 2011)

Decimal CORDIC Rotation based on Selection by Rounding: Algorithm and Architecture. - Amir Kaivani; Ghassem Jaberipur (Comput. J., 2011)

Improving the speed of decimal division. - Amir Kaivani; Adel Hosseiny; Ghassem Jaberipur (IET Comput. Digit. Tech., 2011)

Improved CMOS (4; 2) compressor designs for parallel multipliers. - Abdoreza Pishvaie; Ghassem Jaberipur; Ali Jahanian 001 (Comput. Electr. Eng., 2012)

Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits. - Ghassem Jaberipur; Behrooz Parhami (IET Comput. Digit. Tech., 2012)

Double {0, 1, 2} representation modulo-(2n - 3) adders. - Seyed Hamed Fatemi Langroudi; Ghassem Jaberipur (IWSSIP, 2014)

Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers. - Saeid Gorgin 001; Ghassem Jaberipur; Reza Hashemi Asl (Circuits Syst. Signal Process., 2014)

A ROM-less reverse RNS converter for moduli set {2q±1, 2q±3}. - Ghassem Jaberipur; HamidReza Ahmadifar (IET Comput. Digit. Tech., 2014)

Low area/power decimal addition with carry-select correction and carry-select sum-digits. - Morteza Dorrigiv; Ghassem Jaberipur (Integr., 2014)

Modulo-(2n - 2q - 1) Parallel Prefix Addition via Excess-Modulo Encoding of Residues. - Seyed Hamed Fatemi Langroudi; Ghassem Jaberipur (ARITH, 2015)

A New Residue Number System with 5-Moduli Set: {22q, 2q±3, 2q±1}. - HamidReza Ahmadifar; Ghassem Jaberipur (Comput. J., 2015)

Comment on "High Speed Parallel Decimal Multiplication With Redundant Internal Encodings". - Saeid Gorgin 001; Ghassem Jaberipur (IEEE Trans. Computers, 2015)

(4+2 log n)ΔG Parallel Prefix Modulo-(2n-3) Adder via Double Representation of Residues in [0, 2]. - Ghassem Jaberipur; Seyed Hamed Fatemi Langroudi (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Formulation of Fast Carry Chains Suitable for Efficient Implementation with Majority Elements. - Ghassem Jaberipur; Behrooz Parhami; Dariush Abedi (ARITH, 2016)

Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding. - Morteza Dorrigiv; Ghassem Jaberipur (Comput. Electr. Eng., 2016)

Decimal Goldschmidt: A hardware algorithm for radix-10 division. - Adel Hosseiny; Ghassem Jaberipur (Comput. Electr. Eng., 2016)

Decimal Square Root: Algorithm and Hardware Implementation. - Adel Hosseiny; Ghassem Jaberipur (Circuits Syst. Signal Process., 2016)

Fast low energy RNS comparators for 4-moduli sets {2n±1, 2n, m} with m∈{2n+1±1, 2n-1-1}. - Zeinab Torabi; Ghassem Jaberipur (Integr., 2016)

Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range. - Zeinab Torabi; Ghassem Jaberipur (IEEE Trans. Very Large Scale Integr. Syst., 2016)

(5 + 2⌈log n⌉)ΔG diminished-1 modulo-(2n+1) unified adder/subtractor with full zero handling. - Ghassem Jaberipur; Armin Belghadr (Comput. Electr. Eng., 2017)

Fast Energy Efficient Radix-16 Sequential Multiplier. - Saba Amanollahi; Ghassem Jaberipur (IEEE Embed. Syst. Lett., 2017)

Radix-8 full adder in QCA with single clock-zone carry propagation delay. - Milad Sangsefidi; Dariush Abedi; Ghassem Jaberipur (Microprocess. Microsystems, 2017)

Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems. - Saba Amanollahi; Ghassem Jaberipur (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication. - Saeid Gorgin 001; Ghassem Jaberipur (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata. - Dariush Abedi; Ghassem Jaberipur (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

FIR Filter Realization via Deferred End-Around Carry Modular Addition. - Armin Belghadr; Ghassem Jaberipur (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Extended Redundant-Digit Instruction Set for Energy-Efficient Processors. - Saba Amanollahi; Ghassem Jaberipur (ACM Trans. Embed. Comput. Syst., 2018)

Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies. - Ghassem Jaberipur; Behrooz Parhami; Dariush Abedi (IEEE Trans. Sustain. Comput., 2018)

Modulo-(2^n+3) Parallel Prefix Addition via Diminished-3 Representation of Residues. - Ghassem Jaberipur; Sahar Moradi Cherati (ARITH, 2019)

Impact of diminished-1 encoding on residue number systems arithmetic units and converters. - Ghassem Jaberipur; Armin Belghadr; Saeed Nejati (Comput. Electr. Eng., 2019)

Majority-Logic, its applications, and atomic-scale embodiments. - Behrooz Parhami; Dariush Abedi; Ghassem Jaberipur (Comput. Electr. Eng., 2020)

Fast division in the residue number system {2n + 1, 2n, 2n-1} based on shortcut mixed radix conversion. - Zeinab Torabi; Ghassem Jaberipur; Armin Belghadr (Comput. Electr. Eng., 2020)

Complex exponential functions: A high-precision hardware realization. - Adel Hosseiny; Ghassem Jaberipur (Integr., 2020)

Design of an efficient fully nonvolatile and radiation-hardened majority-based magnetic full adder using FinFET/MTJ. - Sina Bakhtavari Mamaghani; Mohammad Hossein Moaiyeri; Ghassem Jaberipur (Microelectron. J., 2020)

Balanced $(3+2 log n) Delta G$ Adders for Moduli Set $ {{2}^{n+1}, 2^{n}+2^{n-1}-1, 2^{n+1}-1 }$. - Ghassem Jaberipur; Bardia Nadimi (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Efficient variable-coefficient RNS-FIR filters with no restriction on the moduli set. - Armin Belghadr; Ghassem Jaberipur (Signal Image Video Process., 2022)

Up to $8k$8k-bit Modular Montgomery Multiplication in Residue Number Systems With Fast 16-bit Residue Channels. - Zabihollah Ahmadpour; Ghassem Jaberipur (IEEE Trans. Computers, 2022)

Impact of Radix-10 Redundant Digit Set [-6, 9] on Basic Decimal Arithmetic Operations. - Ghassem Jaberipur; Farzad Ghazanfari (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Modulo-(2q - 3) Multiplication with Fully Modular Partial Product Generation and Reduction. - Ghassem Jaberipur; Saeid Gorgin 001; Navid Ahamadian; Jeong-A Lee (ARITH, 2023)

A Parallel Prefix Modulo-(2q + 2q-1 + 1) Adder via Diminished-1 Representation of Residues. - Ghassem Jaberipur; Dariush Badri; Jeong-A Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Montgomery Modular Multiplication via Single-Base Residue Number Systems. - Zabihollah Ahmadpour; Ghassem Jaberipur; Jeong-A Lee (ARITH, 2024)

Sparse Matrix-Vector Multiplication Based on Online Arithmetic. - Sahar Moradi Cherati; Ghassem Jaberipur; Leonel Sousa (IEEE Access, 2024)

RNPE: An MSDF and Redundant Number System-Based DNN Accelerator Engine. - Iraj Moghaddasi; Ghassem Jaberipur; Danial Javaheri; Byeong-Gyu Nam (IEEE Access, 2024)

Modulo-(22n+1) Arithmetic via Two Parallel n-bit Residue Channels. - Ghassem Jaberipur; Bardia Nadimi; Jeong-A Lee (CoRR, 2024)

Forward and Reverse Converters for the Moduli-Set {22q+1,2q+2q-1± 1}. - Ghassem Jaberipur; Bardia Nadimi; R. Kazemi; Jeong-A Lee (CoRR, 2024)

Low-cost constant time signed digit selection for most significant bit first multiplication. - Ghassem Jaberipur; Saeid Gorgin 001; Jeong-A Lee (Microprocess. Microsystems, 2024)

Poster: Integration of Wearable and Affective Computing via Abstraction and Decision Fusion Architecture. - Mohammadreza Najafi; Mohammad K. Fallah; Saeid Gorgin 001; Ghassem Jaberipur; Jeong-A Lee (WoWMoM, 2025)

Balanced Modular Addition for the Moduli Set $ {2^{q},2^{q} mp 1,2^{2q}+1 }${2q,2q∓1,22q+1} via Moduli-($ 2^{q} mp sqrt{-1}$2q∓-1) Adders. - Ghassem Jaberipur; Elham Rahman; Jeong-A Lee (IEEE Trans. Computers, 2025)

Design of energy-efficient and high-speed hybrid decimal adder. - Negin Mashayekhi; Ghassem Jaberipur; Mohammad Reza Reshadinezhad; Shekoofeh Moghimi (J. Supercomput., 2025)

Auto Digit Selection for Most Significant Digit First Multiplication. - Saeid Gorgin 001; Ghassem Jaberipur; Jeong-A Lee; Seokjoo Shin; Jungrae Kim (IEEE Embed. Syst. Lett., 2025)