Non-stationary transport effects in deep sub-micron channel Si mosfets. - Ghavam G. Shahidi (1989)

A half-micron CMOS logic generation. - Charles W. Koburger III; William F. Clark; James W. Adkisson; Eric Adler; Paul E. Bakeman; Albert S. Bergendahl; Alan B. Botula; W. Chang; Bijan Davari; John H. Givens; Howard H. Hansen; Steven J. Holmes; et al. (IBM J. Res. Dev., 1995)

CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications. - Ghavam G. Shahidi; James D. Warnock; James Comfort; Stephen E. Fischer; Patricia A. McFarland; Alexandre Acovic; Terry I. Chappell; Barbara A. Chappell; Tak H. Ning; Carl J. Anderson; Robert H. Dennard; Jack Y.-C. Sun; et al. (IBM J. Res. Dev., 1995)

CMOS scaling for high performance and low power-the next ten years. - Bijan Davari; Robert H. Dennard; Ghavam G. Shahidi (Proc. IEEE, 1995)

250-600 Mhz 12b digital filters in 0.8-0.25um Bulk and SOI CMOS technologies. - Lars E. Thon; Ghavam G. Shahidi; Werner Rausch; Gerald P. Coleman; Denny D. Tang; Dominic Schepis; Ronald Schulz; Fariborz Assadaraghi (ISLPED, 1996)

SRAM bitline circuits on PD SOI: advantages and concerns. - Jente B. Kuang; Somnuk Ratanaphanyarat; Mary Jo Saccamango; Louis L.-C. Hsu; Roy C. Flaker; Lawrence F. Wagner; Shao-Fu Sanford Chu; Ghavam G. Shahidi (IEEE J. Solid State Circuits, 1997)

Device and circuit design issues in SOI technology. - Ghavam G. Shahidi; Atul Ajmera; Fariborz Assaderaghi; Ronald J. Bolam; Harold Hovel; Effendi Leobandung; Werner Rausch; Devendra Sadana; Dominic Schepis; Lawrence F. Wagner; Larry Wissel; Kun Wu; et al. (CICC, 1999)

SOI technology for the GHz era. - Ghavam G. Shahidi (IBM J. Res. Dev., 2002)

Optimizing CMOS technology for maximum performance. - David J. Frank; Wilfried Haensch; Ghavam G. Shahidi; Omer H. Dokumaci (IBM J. Res. Dev., 2006)

Evolution of CMOS Technology at 32 nm and Beyond. - Ghavam G. Shahidi (CICC, 2007)

Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. - Ali Khaki-Firooz; Kangguo Cheng; Basanth Jagannathan; Pranita Kulkarni; Jeffrey W. Sleight; Davood Shahrjerdi; Josephine B. Chang; Sungjae Lee; Junjun Li; Huiming Bu; Robert Gauthier 002; Bruce Doris; et al. (ISSCC, 2010)

From 2D-planar to 3D-non-planar device architecture: A scalable path forward? - Ghavam G. Shahidi (CICC, 2013)

Slow-Down in Power Scaling and the End of Moore's Law? - Ghavam G. Shahidi (VLSI-DAT, 2019)

Chip Power Scaling in Recent CMOS Technology Nodes. - Ghavam G. Shahidi (IEEE Access, 2019)

Chip Power-Frequency Scaling in 10/7nm Node. - Phil Oldiges; Reinaldo A. Vega; Henry K. Utomo; Nick A. Lanzillo; Thomas Wassick; Juntao Li; Junli Wang; Ghavam G. Shahidi (IEEE Access, 2020)

EM-Side-Channel Resistant Symmetric-Key Authentication Mechanism for Small Devices. - Rick Boivie; Charanjit S. Jutla; Daniel Friedman; Ghavam G. Shahidi (IACR Cryptol. ePrint Arch., 2020)