Ghavam G. Shahidi

Orcid: 0000-0002-1208-7540

According to our database1, Ghavam G. Shahidi authored at least 16 papers between 1989 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2004, "For contributions to silicon-on-insulator technology products.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
EM-Side-Channel Resistant Symmetric-Key Authentication Mechanism for Small Devices.
IACR Cryptol. ePrint Arch., 2020

Chip Power-Frequency Scaling in 10/7nm Node.
IEEE Access, 2020

2019
Chip Power Scaling in Recent CMOS Technology Nodes.
IEEE Access, 2019

Slow-Down in Power Scaling and the End of Moore's Law?
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

2013
From 2D-planar to 3D-non-planar device architecture: A scalable path forward?
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2010
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2007
Evolution of CMOS Technology at 32 nm and Beyond.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Optimizing CMOS technology for maximum performance.
IBM J. Res. Dev., 2006

2002
SOI technology for the GHz era.
IBM J. Res. Dev., 2002

1999
Device and circuit design issues in SOI technology.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1997
SRAM bitline circuits on PD SOI: advantages and concerns.
IEEE J. Solid State Circuits, 1997

1996
250-600 Mhz 12b digital filters in 0.8-0.25um Bulk and SOI CMOS technologies.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995
CMOS scaling for high performance and low power-the next ten years.
Proc. IEEE, 1995

CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications.
IBM J. Res. Dev., 1995

A half-micron CMOS logic generation.
IBM J. Res. Dev., 1995

1989
Non-stationary transport effects in deep sub-micron channel Si mosfets.
PhD thesis, 1989


  Loading...