A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. - Rajiv V. Joshi; Wei Hwang; S. C. Wilson; Ghavam V. Shahidi; Ching-Te Chuang (VLSI Design, 2000)

PD/SOI SRAM performance in presence of gate-to-body tunneling current. - Rajiv V. Joshi; Ching-Te Chuang; Samuel K. H. Fung; Fari Assaderaghi; Melanie Sherony; I. Yang; Ghavam V. Shahidi (IEEE Trans. Very Large Scale Integr. Syst., 2003)