A compiler optimization to reduce execution time of loop nest. - Oh-Young Kwon; Gi-Ho Park; Tack-Don Han (SIGARCH Comput. Archit. News, 1996)

Methods to improve performance of instruction prefetching through balanced improvement of two primary performance factors. - Gi-Ho Park; Oh-Young Kwon; Tack-Don Han; Shin-Dug Kim; Sung-Bong Yang (J. Syst. Archit., 1998)

A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure. - Gi-Ho Park; Kil-Whan Lee; Jae-Hyuk Lee; Tack-Don Han; Shin-Dug Kim (LCTES, 2000)

A Dual Data Cache System to Reflect the Principle of Locality Effectively. - Gi-Ho Park; Kil-Whan Lee; Tack-Don Han; Shin-Dug Kim (PDPTA, 2000)

An Advanced Filtering TLB for Low Power Consumption. - Jin-Hyuck Choi; Jung-Hoon Lee; Gi-Ho Park; Shin-Dug Kim (SBAC-PAD, 2002)

Appliaction-Specific Data Cache Systems. - Jung-Hoon Lee; Gi-Ho Park; Shin-Dug Kim (CATA, 2003)

A selective filter-bank TLB system. - Jung-Hoon Lee; Gi-Ho Park; Sung-Bae Park; Shin-Dug Kim (ISLPED, 2003)

An Adaptive Multi-Module Cache with Hardware Prefetching Mechanism for Multimedia Applications. - Jung-Hoon Lee; Gi-Ho Park; Shin-Dug Kim (PDP, 2003)

Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure. - Jung-Wook Park; Gi-Ho Park; Sung-Bae Park; Shin-Dug Kim (ICCD, 2004)

A Low-Power Tournament Branch Predictor. - Sung Woo Chung; Gi-Ho Park; Sung-Bae Park (IEICE Trans. Inf. Syst., 2004)

A Low-Power Branch Predictor for Embedded Processors. - Sung Woo Chung; Gi-Ho Park; Sung-Bae Park (IEICE Trans. Inf. Syst., 2004)

Dynamic and selective low power data TLB system. - Jung-Hoon Lee; Gi-Ho Park; Shin-Dug Kim (Microprocess. Microsystems, 2004)

A new NAND-type flash memory package with smart buffer system for spatial and temporal localities. - Jung-Hoon Lee; Gi-Ho Park; Shin-Dug Kim (J. Syst. Archit., 2005)

p-Refinement Techniques for Vector Finite Elements in Electromagnetics. - Gi-Ho Park (2005)

Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications. - Hoon-Mo Yang; Gi-Ho Park; Shin-Dug Kim (Asia-Pacific Computer Systems Architecture Conference, 2006)

Practice and Experience of an Embedded Processor Core Modeling. - Gi-Ho Park; Sung Woo Chung; Han-Jong Kim; Jung-Bin Im; Jung-Wook Park; Shin-Dug Kim; Sung-Bae Park (HPCC, 2006)

Sim-ARM1136: A case study on the accuracy of the cycle-accurate simulator. - Sung Woo Chung; Gi-Ho Park; Hyo-Joong Suh; Han-Jong Kim; Jung-Bin Im; Jung-Wook Park; Sung-Bae Park (Microprocess. Microsystems, 2006)

A deterministic way-prediction scheme using power-aware replacement policy. - Jung-Wook Park; Gi-Ho Park; Sung-Bae Park; Shin-Dug Kim (Microprocess. Microsystems, 2006)

An efficient scheme for parallelizing fast search algorithm on SIMD architecture in H.264/AVC. - Jung-Min Park; Jung-Wook Park; Cheong-Ghil Kim; Gi-Ho Park; Shin-Dug Kim (PDCS, 2007)

Performance monitor unit design for an AXI-based multi-core SoC platform. - Hyun-min Kyung; Gi-Ho Park; Jong Wook Kwak; WooKyeong Jeong; Tae-Jin Kim; Sung-Bae Park (SAC, 2007)

Cooperative Cache System: A Low Power Cache System for Embedded Processors. - Gi-Ho Park; Kil-Whan Lee; Tack-Don Han; Shin-Dug Kim (IEICE Trans. Electron., 2007)

Power and Skew Aware Point Diffusion Clock Network. - Gunok Jung; Chunghee Kim; Kyoungkuk Chae; Gi-Ho Park; Sung-Bae Park (IEICE Trans. Electron., 2008)

An integrated mapping table for hybrid FTL with fault-tolerant address cache. - Jung-Wook Park; Seung-Ho Park; Gi-Ho Park; Shin-Dug Kim (IEICE Electron. Express, 2009)

Sub-grouped superblock management for high-performance flash storages. - Jung-Wook Park; Gi-Ho Park; Charles C. Weems; Shin-Dug Kim (IEICE Electron. Express, 2009)

Low-Power Embedded Processor Design Using Branch Direction. - Gi-Ho Park; Jung-Wook Park; Gunok Jung; Shin-Dug Kim (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache. - Gi-Ho Park; Jung-Wook Park; Hoi-Jin Lee; Gunok Jung; Sung-Bae Park; Shin-Dug Kim (IEICE Trans. Electron., 2009)

Fully digital clock frequency doubler. - Gunok Jung; Gi-Ho Park; Ukrae Cho; Jae-Cheol Son (IEICE Electron. Express, 2010)

An instruction-systolic programmable shader architecture for multi-threaded 3D graphics processing. - Jung-Wook Park; Hoon-Mo Yang; Gi-Ho Park; Shin-Dug Kim; Charles C. Weems (J. Parallel Distributed Comput., 2010)

Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC). - Hyun-min Kyung; Gi-Ho Park; Jong Wook Kwak; Tae-Jin Kim; Sung-Bae Park (Microprocess. Microsystems, 2010)

Performance and energy-efficiency analysis of hybrid cache memory based on SRAM-MRAM. - Byung-Min Lee; Gi-Ho Park (ISOCC, 2012)

Adaptive replacement policy for hybrid cache architecture. - Ju Hee Choi; Gi-Ho Park (IEICE Electron. Express, 2014)

Data Classification Management with its Interfacing Structure for Hybrid SLC/MLC PRAM Main Memory. - Sung-In Jang; Su-Kyung Yoon; Kihyun Park; Gi-Ho Park; Shin-Dug Kim (Comput. J., 2015)

Demand-Aware NVM Capacity Management Policy for Hybrid Cache Architecture. - Ju Hee Choi; Gi-Ho Park (Comput. J., 2016)

NVM Way Allocation Scheme to Reduce NVM Writes for Hybrid Cache Architecture in Chip-Multiprocessors. - Ju Hee Choi; Gi-Ho Park (IEEE Trans. Parallel Distributed Syst., 2017)

SK Hynix AI-Specific Computing Memory Solution: From AiM Device to Heterogeneous AiMX-xPU System for Comprehensive LLM Inference. - Guhyun Kim; Jinkwon Kim; Nahsung Kim; Woojae Shin; Jongsoon Won; Hyunha Joo; Haerang Choi; Byeongju An; Gyeongcheol Shin; Dayeon Yun; Jeongbin Kim 001; Changhyun Kim; et al. (HCS, 2024)