Implementation of the super-systolic array for convolution. - Jae-Jin Lee; Gi-Yong Song (ASP-DAC, 2003)

Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier. - Jae-Jin Lee; Gi-Yong Song (FPGA, 2004)

Design of an application-specific PLD architecture. - Jae-Jin Lee; Gi-Yong Song (ASP-DAC, 2005)

A New Application-Specific PLD Architecture. - Jae-Jin Lee; Gi-Yong Song (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

High-Level Synthesis Using SPARK and Systolic Array. - Jae-Jin Lee; Gi-Yong Song (ARC, 2006)

Super Semi-systolic Array-Based Application-Specific PLD Architecture. - Jae-Jin Lee; Gi-Yong Song (ARC, 2006)

Design of a Reversible PLD Architecture. - Jae-Jin Lee; Dong-Guk Hwang; Gi-Yong Song (ARC, 2007)

SystemVerilog-Based Verification Environment Employing Multiple Inheritance of SystemC. - Myoung-Keun You; Gi-Yong Song (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Design and verification of an application-specific PLD using VHDL and SystemVerilog. - Jae-Jin Lee; Young-Jin Oh; Gi-Yong Song (ASICON, 2011)