Junction leakage current degradation under high temperature reverse-bias stress induced by band-defect-band tunnelling in power VDMOS. - Giacomo Barletta; Giuseppe Currò (Microelectron. Reliab., 2005)

Evaluation of the generation mechanisms at surface and in the bulk of the silicon by current transient technique. - Giacomo Barletta; Giuseppe Currò (Microelectron. Reliab., 2007)

Study of gate leakage mechanism in advanced charge-coupled MOSFET (CC-MOSFET) technology. - Giacomo Barletta; V. C. Ngwan (Microelectron. Reliab., 2016)

Investigation of degradation mechanisms in low-voltage p-channel power MOSFETs under High Temperature Gate Bias stress. - Paolo Magnone; Giacomo Barletta; A. Magrì (Microelectron. Reliab., 2018)