A framework for integrated monitoring of real-time embedded SoC. - Giacomo Valente (FPL, 2015)

Hardware performance sniffers for embedded systems profiling. - Andrea Moro; Fabio Federici; Giacomo Valente; Luigi Pomante; Marco Faccio; Vittoriano Muttillo (WISES, 2015)

A Flexible Profiling Sub-System for Reconfigurable Logic Architectures. - Giacomo Valente; Vittoriano Muttillo; Luigi Pomante; Fabio Federici; Marco Faccio; Andrea Moro; Serenella Ferri; Carlo Tieri (PDP, 2016)

Design and validation of multi-core embedded systems under time-to-prototype and high performance constraints. - Marco Faccio; Fabio Federici; Giuseppe Marini; Vittoriano Muttillo; Luigi Pomante; Giacomo Valente (RTSI, 2016)

A design methodology for soft-core platforms on FPGA with SMP Linux, OpenMP support, and distributed hardware profiling system. - Vittoriano Muttillo; Giacomo Valente; Fabio Federici; Luigi Pomante; Marco Faccio; Carlo Tieri; Serenella Ferri (EURASIP J. Embed. Syst., 2016)

Simulation-Based Analysis of a Hardware Mechanism to Support Isolation in Mixed-Criticality Network on Chip. - Fabio Federici; Mattia Micozzi; Vittoriano Muttillo; Luigi Pomante; Giacomo Valente (EMS, 2017)

An Efficient Performance-Driven Approach for HW/SW Co-Design. - Daniele Di Pompeo; Emilio Incerto; Vittoriano Muttillo; Luigi Pomante; Giacomo Valente (ICPE, 2017)

Time Bands: A Software Approach for Timing Analysis on Resource Constrained Systems. - Giacomo Valente; Marco Rotondi; Vittoriano Muttillo (ICPE, 2017)

A HW/SW unified approach for embedded systems monitoring. - Giacomo Valente (2017)

Design Space Exploration for Mixed-Criticality Embedded Systems Considering Hypervisor-Based SW Partitions. - Vittoriano Muttillo; Giacomo Valente; Luigi Pomante (DSD, 2018)

Criticality-driven Design Space Exploration for Mixed-Criticality Heterogeneous Parallel Embedded Systems. - Vittoriano Muttillo; Giacomo Valente; Luigi Pomante (PARMA-DITAM@HiPEAC, 2018)

HEPSIM: An ESL HW/SW co-simulator/analysis tool for heterogeneous parallel embedded systems. - Daniele Ciambrone; Vittoriano Muttillo; Luigi Pomante; Giacomo Valente (MECO, 2018)

Injecting hypervisor-based software partitions into Design Space Exploration activities considering mixed-criticality requirements. - Vittoriano Muttillo; Giacomo Valente (MECO, 2018)

HEPSYCODE-RT: a Real-Time Extension for an ESL HW/SW Co-Design Methodology. - Vittoriano Muttillo; Giacomo Valente; Daniele Ciambrone; Vincenzo Stoico; Luigi Pomante (RAPIDO, 2018)

Criticality-aware Design Space Exploration for Mixed-Criticality Embedded Systems. - Vittoriano Muttillo; Giacomo Valente; Luigi Pomante (ICPE Companion, 2018)

CC4CS: an Off-the-Shelf Unifying Statement-Level Performance Metric for HW/SW Technologies. - Vittoriano Muttillo; Giacomo Valente; Luigi Pomante; Vincenzo Stoico; Fausto D'Antonio; Fabio Salice (ICPE Companion, 2018)

An Intelligent Informative Totem Application Based on Deep CNN in Edge Regime. - Paolo Giammatteo; Giacomo Valente; Alessandro D'Ortenzio (ApplePies, 2019)

Self-adaptive loop for CPSs: is the Dynamic Partial Reconfiguration profitable? - Gabriella D'Andrea; Tania Di Mascio; Giacomo Valente (MECO, 2019)

Layering the monitoring action for improved flexibility and overhead control: work-in-progress. - Giacomo Valente; Tiziana Fanni; Carlo Sau; Francesco Di Battista (CODES+ISSS, 2020)

An ESL Methodology for HW/SW Co-Design of Monitorable Embedded Systems: the "Design for Monitorability" Project - Work-in-Progress. - Giacomo Valente; Tania Di Mascio; Luigi Pomante; Vincenzo Stoico (CODES+ISSS, 2020)

Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow. - Vittoriano Muttillo; Giacomo Valente; Luigi Pomante; Hector Posadas; Javier Merino; Eugenio Villar (DSD, 2020)

Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project. - Luigi Pomante; Francesca Palumbo; Claudia Rinaldi; Giacomo Valente; Carlo Sau; Tiziana Fanni; Frank van der Linden 001; Twan Basten; Marc Geilen; Geran Peeren; Jirí Kadlec; Pekka Jääskeläinen; et al. (DSD, 2020)

Work-In-Progress: Cyber-Physical Systems and Dynamic Partial Reconfiguration Scalability: opportunities and challenges. - Gabriella D'Andrea; Giacomo Valente (RTSS, 2020)

MONICA Vision: An Approach, a Model and the Interactive Tools for Cyber-Physical Systems Designers. - Tania Di Mascio; Federica Caruso; Laura Tarantino; Giacomo Valente (CHItaly, 2021)

An Investigation of Dynamic Partial Reconfiguration Offloading in Hard Real-Time Systems. - Gabriella D'Andrea; Giacomo Valente; Luigi Pomante; Tania Di Mascio (DSD, 2021)

MONICA "On-the-Job" Technology-Enhanced Learning Environment: An Empirical Evaluation. - Federica Caruso; Tania Di Mascio; Sara Peretti; Luigi Pomante; Giacomo Valente (MIS4TEL, 2021)

Dynamic Partial Reconfiguration Profitability for Real-Time Systems. - Giacomo Valente; Tania Di Mascio; Luigi Pomante; Gabriella D'Andrea (IEEE Embed. Syst. Lett., 2021)

A Composable Monitoring System for Heterogeneous Embedded Platforms. - Giacomo Valente; Tiziana Fanni; Carlo Sau; Tania Di Mascio; Luigi Pomante; Francesca Palumbo (ACM Trans. Embed. Comput. Syst., 2021)

Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project. - Carlo Sau; Claudia Rinaldi; Luigi Pomante; Francesca Palumbo; Giacomo Valente; Tiziana Fanni; Marcos Martinez de Alejandro; Frank van der Linden 001; Twan Basten; Marc Geilen; Geran Peeren; Jirí Kadlec; et al. (Microprocess. Microsystems, 2021)

Sentient Spaces: Intelligent Totem Use Case in the ECSEL FRACTAL Project. - Federica Caruso; Tania Di Mascio; Daniele Frigioni; Luigi Pomante; Giacomo Valente; Stefano Delucchi; Paolo Burgio; Manuel Di Frangia; Luca Paganin; Chiara Garibotto; Damiano Vallocchia (DSD, 2022)

Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs. - Gianluca Brilli; Giacomo Valente; Alessandro Capotondi; Paolo Burgio; T. Di Masciov; Paolo Valente; Andrea Marongiu (DAC, 2023)

SystemC-based Co-Simulation/Analysis for System-Level Hardware/Software Co-Design. - Vittoriano Muttillo; Luigi Pomante; Marco Santic; Giacomo Valente (Comput. Electr. Eng., 2023)

SLIDE-x-ML: System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations. - Vittoriano Muttillo; Vincenzo Stoico; Marco Santic; Giacomo Valente; Luigi Pomante; Daniele Frigioni (ICCD, 2024)

Invited Paper: On the Granularity of Bandwidth Regulation in FPGA-Based Heterogeneous Systems on Chip. - Gianluca Brilli; Giacomo Valente; Alessandro Capotondi; Tania Di Mascio; Andrea Marongiu (WCET, 2024)

Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection. - Giacomo Valente; Vittoriano Muttillo; Fabio Federici; Luigi Pomante; Tania Di Mascio (IEEE Embed. Syst. Lett., 2024)

Multi-Context Execution on a RISC-V Core for Mixed-Criticality Systems. - Leonardo Fazzini; Giacomo Valente; Fabio Federici; Matthew P. Corbett; Tania Di Mascio (ETS, 2025)

System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric. - Vittoriano Muttillo; Vincenzo Stoico; Giacomo Valente; Marco Santic; Luigi Pomante; Daniele Frigioni (PARMA-DITAM, 2025)

Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-Based Heterogeneous SoCs. - Giacomo Valente; Gianluca Brilli; Tania Di Mascio; Alessandro Capotondi; Paolo Burgio; Paolo Valente; Andrea Marongiu (IEEE Trans. Parallel Distributed Syst., 2025)