RNS Fourier transforms. - Pietro Burrascano; Gian Carlo Cardarilli; Roberto Lojacono; Giuseppe Martinelli; Mario Salerno (ICASSP, 1988)

RNS approach to fast dividers. - Gian Carlo Cardarilli; Roberto Lojacono; Mario Salerno (ICASSP, 1989)

RNS approach to full parallel linear combinators. - Mario Salerno; Gian Carlo Cardarilli; Roberto Lojacono; F. Sargeni (ICASSP, 1990)

Grid Generation and Verification for 3-D Device Simulation. - Gian Carlo Cardarilli; Marcello Salmeri; Adelio Salsano (EUROSIM, 1992)

Letter limit cycles in residue number system filters. - Gian Carlo Cardarilli; Martin Hasler (Eur. Trans. Telecommun., 1992)

A High Speed Reed-Solomon Encoder-Decoder for Fault Tolerant Solid State Disks. - Gian Carlo Cardarilli; M. Di Zenzo; Pat O. Pistilli; Adelio Salsano (DFT, 1993)

Analysis and implementation of a VLSI neural network. - Gian Carlo Cardarilli; Gabriele Di Stefano; G. Fabrizi; P. Marinucci (ICNN, 1995)

A low-voltage reduced-power constant-gm rail-to-rail fully differential CMOS op-amp. - Giuseppe Ferri; Willy Sansen; Gian Carlo Cardarilli (ICECS, 1996)

VLSI implementation of a real time fuzzy processor. - Gian Carlo Cardarilli; Marco Re; Roberto Lojacono (J. Intell. Fuzzy Syst., 1998)

Failure Tests on 64 Mb SDRAM in Radiation Environment. - Stefano Bertazzoni; Gian Carlo Cardarilli; D. Piergentili; Marcello Salmeri; Adelio Salsano; Domenico Di Giovenale; G. C. Grande; P. Marinucci; S. Sperandei; S. Bartalucci; G. Mazzenga; Marco Ricci 003; et al. (DFT, 1999)

Design of Fault-Tolerant Solid State Mass Memory. - Gian Carlo Cardarilli; Stefano Bertazzoni; Marcello Salmeri; Adelio Salsano; P. Marinucci (DFT, 1999)

Bipolar and CMOS low voltage-supply reduced-power voltage followers. - Giuseppe Ferri; Franco Alfonsetti; Gian Carlo Cardarilli; Marco Re (ICECS, 1999)

Analysis of the quantization noise effects on the SQNR behaviour in analog to digital conversion. - Alberto L. Sangiovanni-Vincentelli; Marco Re; Luciano Lavagno; Gian Carlo Cardarilli; Roberto Lojacono (ISCAS (2), 1999)

A Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture. - Gian Carlo Cardarilli; Adelio Salsano; P. Marinucci; Marco Ottavi (DFT, 2000)

A novel bacterial algorithm to extract the rule base from a training set. - Marcello Salmeri; Marco Re; Enrico Petrongari; Gian Carlo Cardarilli (FUZZ-IEEE, 2000)

Development of an evaluation model for the design of fault-tolerant solid state mass memory. - Gian Carlo Cardarilli; Panfilo Marinucci; Adelio Salsano (ISCAS, 2000)

FPGA implementation of a demux based on a multirate filter bank. - Marco Re; Gian Carlo Cardarilli; Andrea Del Re; Roberto Lojacono (ISCAS, 2000)

A CAD environment for fuzzy systems HW/SW mapping. - Marco Re; Marcello Salmeri; Gian Carlo Cardarilli (ISCAS, 2000)

Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines. - Marco Ottavi; Gian Carlo Cardarilli; D. Cellitti; Salvatore Pontarelli; Marco Re; Adelio Salsano (DFT, 2001)

System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology. - Salvatore Pontarelli; Gian Carlo Cardarilli; A. Malvoni; Marco Ottavi; Marco Re; Adelio Salsano (DFT, 2001)

Tradeoffs between residue number system and traditional FIR filters. - Alberto Nannarelli; Marco Re; Gian Carlo Cardarilli (ISCAS (2), 2001)

Development of a dynamic routing system for a fault tolerant solid state mass memory. - Marco Ottavi; Gian Carlo Cardarilli; Panfilo Marinucci; Salvatore Pontarelli; Adelio Salsano (ISCAS (4), 2001)

FPGA realization of RNS to binary signed conversion architecture. - Marco Re; Alberto Nannarelli; Gian Carlo Cardarilli; Roberto Lojacono (ISCAS (4), 2001)

Bit Flip Injection in Processor-Based Architectures: A Case Study. - Gian Carlo Cardarilli; F. Kaddour; A. Leandri; Marco Ottavi; Salvatore Pontarelli; Raoul Velazco (IOLTW, 2002)

Power characterization of digital filters implemented on FPGA. - Gian Carlo Cardarilli; Andrea Del Re; Alberto Nannarelli; Marco Re (ISCAS (5), 2002)

A self-checking cell logic block for fault tolerant FPGAs. - Salvatore Pontarelli; Gian Carlo Cardarilli; A. Leandri; Marco Ottavi; Marco Re; Adelio Salsano (ISCAS (4), 2002)

Efficient Implementation of a Demultiplexer Based on a Multirate Filter Bank for the Skyplex Satellites DVB System. - Marco Re; Andrea Del Re; Gian Carlo Cardarilli (VLSI Design, 2002)

Error Detection in Signed Digit Arithmetic Circuit with Parity Checker. - Gian Carlo Cardarilli; Marco Ottavi; Salvatore Pontarelli; Marco Re; Adelio Salsano (DFT, 2003)

A fault tolerant hardware based file system manager for solid state mass memory. - Gian Carlo Cardarilli; Marco Ottavi; Salvatore Pontarelli; Marco Re; Adelio Salsano (ISCAS (5), 2003)

IP based reconfigurable digital platform for satellite communications. - Gian Carlo Cardarilli; Andrea Del Re; Marco Re (ISCAS (2), 2003)

Power-delay tradeoffs in residue number system. - Alberto Nannarelli; Gian Carlo Cardarilli; Marco Re (ISCAS (5), 2003)

Design of a fault tolerant solid state mass memory. - Gian Carlo Cardarilli; A. Leandri; P. Marinucci; Marco Ottavi; Salvatore Pontarelli; Marco Re; Adelio Salsano (IEEE Trans. Reliab., 2003)

Data Integrity Evaluations of Reed Solomon Codes for Storage Systems. - Gian Carlo Cardarilli; Marco Ottavi; Salvatore Pontarelli; Marco Re; Adelio Salsano (DFT, 2004)

A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities. - Gian Carlo Cardarilli; Marco Ottavi; Salvatore Pontarelli; Marco Re; Adelio Salsano (IOLTS, 2004)

Low-power implementation of polyphase filters in Quadratic Residue Number system. - Gian Carlo Cardarilli; Andrea Del Re; Alberto Nannarelli; Marco Re (ISCAS (2), 2004)

A Self Checking Reed Solomon Encoder: Design and Analysis. - Gian Carlo Cardarilli; Salvatore Pontarelli; Marco Re; Adelio Salsano (DFT, 2005)

FPGA oriented design of parity sharing RS codecs. - Gian Carlo Cardarilli; Salvatore Pontarelli; Marco Re; Adelio Salsano (DFT, 2005)

FPGA implementation of a general purpose HMM processor based on token passing algorithm. - D. Bianchi; Gian Carlo Cardarilli; Andrea Del Re; A. Malatesta; Marco Re (ECCTD, 2005)

Design of a Self Checking Reed Solomon Encoder. - Gian Carlo Cardarilli; Salvatore Pontarelli; Marco Re; Adelio Salsano (IOLTS, 2005)

Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. - Gian Carlo Cardarilli; Andrea Del Re; Alberto Nannarelli; Marco Re (ISCAS (2), 2005)

Evaluating the Data Integrity of Memory Systems by Configurable Markov Models. - Marco Ottavi; Luca Schiano; Fabrizio Lombardi; Salvatore Pontarelli; Gian Carlo Cardarilli (ISVLSI, 2005)

A Comparative Evaluation of Designs for Reliable Memory Systems. - Gian Carlo Cardarilli; Fabrizio Lombardi; Marco Ottavi; Salvatore Pontarelli; Marco Re; Adelio Salsano (J. Electron. Test., 2005)

Localization of Faults in Radix-n Signed Digit Adders. - Gian Carlo Cardarilli; Marco Ottavi; Salvatore Pontarelli; Marco Re; Adelio Salsano (IOLTS, 2006)

Concurrent error detection in Reed Solomon decoders. - Gian Carlo Cardarilli; Salvatore Pontarelli; Marco Re; Adelio Salsano (ISCAS, 2006)

Fault tolerant design of signed digit based FIR filters. - Gian Carlo Cardarilli; Salvatore Pontarelli; Marco Re; Adelio Salsano (ISCAS, 2006)

Optimized QPSK modulator for DVB-S applications. - Gian Carlo Cardarilli; Andrea Del Re; Marco Re; Lorenzo Simone (ISCAS, 2006)

Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders. - Gian Carlo Cardarilli; Marco Ottavi; Salvatore Pontarelli; Marco Re; Adelio Salsano (IEEE Trans. Computers, 2006)

Optimization of Self Checking FIR filters by means of Fault Injection Analysis. - Salvatore Pontarelli; Luca Sterpone; Gian Carlo Cardarilli; Marco Re; Matteo Sonza Reorda; Adelio Salsano; Massimo Violante (DFT, 2007)

Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. - Salvatore Pontarelli; Luca Sterpone; Gian Carlo Cardarilli; Marco Re; Matteo Sonza Reorda; Adelio Salsano; Massimo Violante (IOLTS, 2007)

Low-power adaptive filter based on RNS components. - G. L. Bernocchi; Gian Carlo Cardarilli; Andrea Del Re; Alberto Nannarelli; Marco Re (ISCAS, 2007)

Analysis of Errors and Erasures in Parity Sharing RS Codecs. - Gian Carlo Cardarilli; Salvatore Pontarelli; Marco Re; Adelio Salsano (IEEE Trans. Computers, 2007)

Concurrent Error Detection in Reed-Solomon Encoders and Decoders. - Gian Carlo Cardarilli; Salvatore Pontarelli; Marco Re; Adelio Salsano (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Reducing power dissipation in pipelined accumulators. - Gian Carlo Cardarilli; Alberto Nannarelli; Marco Re (ACSCC, 2008)

A Software Defined Radio Architecture for a Regenerative Onboard processor. - Francesco Iacomacci; Catherine Morlet; Francesca Autelitano; Gian Carlo Cardarilli; Marco Re; Enrico Petrongari; Gino Bogo; Mario Franceschelli (AHS, 2008)

A Novel Error Detection and Correction Technique for RNS Based FIR Filters. - Salvatore Pontarelli; Gian Carlo Cardarilli; Marco Re; Adelio Salsano (DFT, 2008)

A full-adder based reconfigurable architecture for fine grain applications: ADAPTO. - Gian Carlo Cardarilli; Luca Di Nunzio; Marco Re (ICECS, 2008)

On the use of signed digit arithmetic for the new 6-inputs LUT based FPGAs. - Gian Carlo Cardarilli; Salvatore Pontarelli; Marco Re; Adelio Salsano (ICECS, 2008)

Totally Fault Tolerant RNS Based FIR Filters. - Salvatore Pontarelli; Gian Carlo Cardarilli; Marco Re; Adelio Salsano (IOLTS, 2008)

ADAPTO: full-adder based reconfigurable architecture for bit level operations. - Gian Carlo Cardarilli; Luca Di Nunzio; Marco Re; Alberto Nannarelli (ISCAS, 2008)

On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters. - Gian Carlo Cardarilli; Alberto Nannarelli; Marco Re (VLSI-SoC (Selected Papers), 2008)

Analysis and Evaluations of Reliability of Reconfigurable FPGAs. - Salvatore Pontarelli; Marco Ottavi; Vamsi Vankamamidi; Gian Carlo Cardarilli; Fabrizio Lombardi; Adelio Salsano (J. Electron. Test., 2008)

Describing Different Brain Computer Interface Systems Through a Unique Model: A UML Implementation. - Lucia Rita Quitadamo; Maria Grazia Marciani; Gian Carlo Cardarilli; Luigi Bianchi (Neuroinformatics, 2008)

Error Correction Codes for SEU and SEFI Tolerant Memory Systems. - Salvatore Pontarelli; Gian Carlo Cardarilli; Marco Re; Adelio Salsano (DFT, 2009)

Error detection in addition chain based ECC Point Multiplication. - Salvatore Pontarelli; Gian Carlo Cardarilli; Marco Re; Adelio Salsano (IOLTS, 2009)

Arithmetic/Logic Blocks for Fine-grained Reconfigurable Units. - Gian Carlo Cardarilli; Luca Di Nunzio; Marco Re (ISCAS, 2009)

Speed-up of RISC Processor Computation using ADAPTO. - Gian Carlo Cardarilli; Luca Di Nunzio; Marco Re (ISCAS, 2009)

Improved Large-signal Model for Vacuum Triodes. - Gian Carlo Cardarilli; Marco Re; Leonardo Di Carlo (ISCAS, 2009)

VLSI implementation of reconfigurable cells for RFU in embedded processors. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Christian Lenci; Marco Re (ICECS, 2010)

Algorithm acceleration on LEON-2 processor using a reconfigurable bit manipulation unit. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re (WISES, 2010)

Fine-grain Reconfigurable Functional Unit for embedded processors. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re (ACSCC, 2011)

Partial reconfiguration in the implementation of autonomous radio receivers for space. - Gian Carlo Cardarilli; Marco Re; Ilir Shuli; Lorenzo Simone (ReCoSoC, 2011)

Imprecise arithmetic for low power image processing. - Pietro Albicocco; Gian Carlo Cardarilli; Alberto Nannarelli; Massimo Petricca; Marco Re (ACSCC, 2012)

Karatsuba implementation of FIR filters. - Pietro Albicocco; Gian Carlo Cardarilli; Salvatore Pontarelli; Marco Re (ACSCC, 2012)

Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re; Ruby B. Lee (ACSCC, 2012)

Power efficient design of parallel/serial FIR filters in RNS. - Massimo Petricca; Pietro Albicocco; Gian Carlo Cardarilli; Alberto Nannarelli; Marco Re (ACSCC, 2012)

Optimized Implementation of RNS FIR Filters Based on FPGAs. - Salvatore Pontarelli; Gian Carlo Cardarilli; Marco Re; Adelio Salsano (J. Signal Process. Syst., 2012)

Truncated multipliers through power-gating for degrading precision arithmetic. - Pietro Albicocco; Gian Carlo Cardarilli; Alberto Nannarelli; Massimo Petricca; Marco Re (ACSSC, 2013)

Spiking neural networks based on LIF with latency: Simulation and synchronization effects. - Gian Carlo Cardarilli; Alessandro Cristini; Luca Di Nunzio; Marco Re; Mario Salerno; Gianluca Susi (ACSSC, 2013)

Compressive sensing spectrum analysis for space autonomous radio receivers. - Gian Carlo Cardarilli; Marco Re; Ilir Shuli; Lorenzo Simone (ACSSC, 2013)

A Reconfigurable Functional Unit for Modular Operations. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Salvatore Pontarelli; Marco Re (ApplePies, 2013)

High Performance Bit-Stream Decompressor for Partial Reconfigurable FPGAs. - Gian Carlo Cardarilli; Marco Re; Ilir Shuli (ApplePies, 2013)

TDES cryptography algorithm acceleration using a reconfigurable functional unit. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re (ICECS, 2014)

Twenty years of research on RNS for DSP: Lessons learned and future perspectives. - Pietro Albicocco; Gian Carlo Cardarilli; Alberto Nannarelli; Marco Re (ISIC, 2014)

A Wireless Sensor Node Based on Microbial Fuel Cell. - Simone Acciarito; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re (ApplePies, 2015)

A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration. - Gian Carlo Cardarilli; Leonardo Di Carlo; Alberto Nannarelli; Federico Maria Pandolfi; Marco Re (ISSPIT, 2015)

Characterization of RNS multiply-add units for power efficient DSP. - Gian Carlo Cardarilli; Alberto Nannarelli; Massimo Petricca; Marco Re (MWSCAS, 2015)

High Dynamic Optimized Carrier Loop Improvement for Tracking Doppler Rates. - Amirhossein Fereidountabar; Gian Carlo Cardarilli; Marco Re (J. Electr. Comput. Eng., 2015)

Dynamically-loaded Hardware Libraries (HLL) technology for audio applications. - A. Esposito; Andrea Lomuscio; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re (ACSSC, 2016)

Compressive Sensing Reconstruction for Complex System: A Hardware/Software Approach. - Simone Acciarito; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Gaurav Mani Khanal; Marco Re (ApplePies, 2016)

ZnO-rGO Composite Thin Film Resistive Switching Device: Emulating Biological Synapse Behavior. - Gaurav Mani Khanal; Simone Acciarito; Gian Carlo Cardarilli; Abhishek Chakraborty; Luca Di Nunzio; Rocco Fazzolari; Alessandro Cristini; Gianluca Susi; Marco Re (ApplePies, 2016)

Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams. - Filippo Giuliani; Marco Ottavi; Gian Carlo Cardarilli; Marco Re; Luca Di Nunzio; Rocco Fazzolari; Antimo Bruno; Francesco Zuliani (DFT, 2016)

A hardware framework for on-chip FPGA acceleration. - Andrea Lomuscio; Gian Carlo Cardarilli; Alberto Nannarelli; Marco Re (ISIC, 2016)

Digital Architecture of Next Generation Spacecraft Tracker Based on Wideband ∆DOR. - Simone Acciarito; Gian Carlo Cardarilli; Gaurav Mani Khanal; Marco Matta; Marco Re; Francesca Silvestri; Sergio Spanò; Dario Gelfusa; Lorenzo Simone (ApplePies, 2017)

A Wireless Sensor Node for Acoustic Emission Non-destructive Testing. - Gian Carlo Cardarilli; Luca Di Nunzio; Federico Massimi; Rocco Fazzolari; Carlo De Petris; Giuseppe Augugliaro; Canio Mennuti (ApplePies, 2017)

FPGA Implementation of a Low-Power QRS Extractor. - Francesca Silvestri; Simone Acciarito; Gian Carlo Cardarilli; Gaurav Mani Khanal; Luca Di Nunzio; Rocco Fazzolari; Marco Re (ApplePies, 2017)

A new electric encoder position estimator based on the Chinese Remainder Theorem for the CMG performance improvements. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Luca Gerardi; Marco Re; Giovanni Campolo; Domenico Cascone (ISCAS, 2017)

Robust throughput boosting for low latency dynamic partial reconfiguration. - Alberto Nannarelli; Marco Re; Gian Carlo Cardarilli; Luca Di Nunzio; M. Spaziani Brunella; Rocco Fazzolari; F. Carbonari (SoCC, 2017)

Hardware design of LIF with Latency neuron model with memristive STDP synapses. - Simone Acciarito; Gian Carlo Cardarilli; Alessandro Cristini; Luca Di Nunzio; Rocco Fazzolari; Gaurav Mani Khanal; Marco Re; Gianluca Susi (Integr., 2017)

A Power Efficient Digital Front-End for Cognitive Radio Systems. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re (ACSSC, 2018)

Comparison and Implementation of Variable Fractional Delay Filters for Wideband Digital Beamforming. - Gian Carlo Cardarilli; Daniele Giardino; Marco Matta; Marco Re; Francesca Silvestri; Lorenzo Simone; Sergio Spanò (ApplePies, 2018)

Efficient Ensemble Machine Learning Implementation on FPGA Using Partial Reconfiguration. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Marco Re; Francesca Silvestri; Sergio Spanò (ApplePies, 2018)

Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility. - Marco Ottavi; Dario Asciolla; Tiziano Fiorucci; Elena Grosso; Carla Marzullo; Alessandro Scaramella; Simone Stramaccioni; Alessia Zibecchi; Carla Andreani; Gian Carlo Cardarilli; Carlo Cazzaniga; Luca Di Nunzio; et al. (DTIS, 2018)

Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Dario Gelfusa; Marco Matta; Alberto Nannarelli; Marco Re; Lorenzo Simone; Sergio Spanò (SMACD, 2018)

Channel estimation for high speed unmanned aerial vehicle with STBC in MIMO radio links. - Amirhossein Fereidountabar; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari (Int. J. Comput. Vis. Robotics, 2018)

Approximated Canonical Signed Digit for Error Resilient Intelligent Computation. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re (ACSSC, 2019)

Acoustic Emissions Detection and Ranging of Cracks in Metal Tanks Using Deep Learning. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Marco Re; Sergio Spanò (ApplePies, 2019)

Digital Signal Processing Accelerator for RISC-V. - L. Calicchia; V. Ciotoli; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re (ICECS, 2019)

A Reinforcement Learning-Based QAM/PSK Symbol Synchronizer. - Marco Matta; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Alberto Nannarelli; Marco Re; Sergio Spanò (IEEE Access, 2019)

An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm. - Sergio Spanò; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Alberto Nannarelli; Marco Re (IEEE Access, 2019)

FPGA Implementation of Q-RTS for Real-Time Swarm Intelligence Systems. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Alberto Nannarelli; Marco Re; Sergio Spanò (ACSSC, 2020)

An Action-Selection Policy Generator for Reinforcement Learning Hardware Accelerators. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Matta; Marco Re; Sergio Spanò (ApplePies, 2020)

N-Dimensional Approximation of Euclidean Distance. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re; Sergio Spanò (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

AW-SOM, an Algorithm for High-Speed Learning in Hardware Self-Organizing Maps. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re; Sergio Spanò (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

"MR Q-Learning" Algorithm for Efficient Hardware Implementations. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Dario Natale; Marco Re; Sergio Spanò (ACSCC, 2021)

A M-PSK Timing Recovery Loop Based on Q-Learning. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Matteo Guadagno; Marco Re; Sergio Spanò (ApplePies, 2021)

Design and FPGA Implementation of a Low Power OFDM Transmitter for Narrow-Band IoT. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Riccardo La Cesa; Marco Re (SYSTEM, 2021)

A Parallel Hardware Implementation for 2-D Hierarchical Clustering Based on Fuzzy Logic. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Massimo Panella; Marco Re; Antonello Rosato; Sergio Spanò (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

M-PSK Demodulator With Joint Carrier and Timing Recovery. - Daniele Giardino; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Marco Re; Sergio Spanò (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Automatic IP Core Generator for FPGA-Based Q-Learning Hardware Accelerators. - Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re; Sergio Spanò (ApplePies, 2022)

AI-Based Sound Event Detection on IoT Nodes: Requirements Evaluation. - D. Errico; Marco Re; V. Colombo; Gian Carlo Cardarilli; M. Martina; M. Ruo Roch (ApplePies, 2022)

Profiling of CNNs using the MATLAB FPGA-based Deep Learning Processor. - Sergio Spanò; Lorenzo Canese; Gian Carlo Cardarilli (PRIME, 2022)

FPGA-Based Road Crack Detection Using Deep Learning. - Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re; Sergio Spanò (SYSINT, 2022)

An FPGA-based multi-agent Reinforcement Learning timing synchronizer. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Re; Andrea Ricci; Sergio Spanò (Comput. Electr. Eng., 2022)

Sensing and Detection of Traffic Signs Using CNNs: An Assessment on Their Performance. - Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Hamed Famil Ghadakchi; Marco Re; Sergio Spanò (Sensors, 2022)

Design Space Exploration Based Methodology for Residue Number System Digital Filters Implementation. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Alberto Nannarelli; Massimo Petricca; Marco Re (IEEE Trans. Emerg. Top. Comput., 2022)

A Hardware-Oriented QAM Demodulation Method Driven by AW-SOM Machine Learning. - Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re; Sergio Spanò (ACSSC, 2023)

Tunable Floating Point for High Quality Audio Systems: The Sound of Numbers. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Riccardo La Cesa; Alberto Nannarelli; Marco Re (ACSSC, 2023)

A RISC-V Hardware Accelerator for Q-Learning Algorithm. - Damiano Angeloni; Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Marco Re; Sergio Spanò (ApplePies, 2023)

An RNS-Based Initial Absolute Position Estimator for Electrical Encoders. - Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Re; Alberto Nannarelli; Sergio Spanò (IEEE Access, 2023)

Efficient Digital Implementation of a Multirate-Based Variable Fractional Delay Filter for Wideband Beamforming. - Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Re; Sergio Spanò (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A RISC-V Hardware Accelerator for AW-SOM Machine Learning. - Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Riccardo La Cesa; Mariano Neroni; Simone Pace; Sergio Spanò (IEEECONF, 2024)

Onboard FPGA AI/ML Processing on Landsat-8 Satellite Images: A Case Study of Wildfires Detection. - Lorenzo Canese; Gian Carlo Cardarilli; Giuseppe D'Angelo; Luca Di Nunzio; Piero Gabellini; Riccardo La Cesa; Marco Re; Sergio Spanò (ApplePies, 2024)

Automatic Tunable Floating-Point Format Selection in a RISC-V Ecosystem. - Alberto Nannarelli; Marco Re; Gian Carlo Cardarilli; Luca Di Nunzio; Sergio Spanò (ApplePies, 2024)

Design Space Exploration for Edge Machine Learning Featured by MathWorks FPGA DL Processor: A Survey. - Stefano Bertazzoni; Lorenzo Canese; Gian Carlo Cardarilli; Luca Di Nunzio; Rocco Fazzolari; Marco Re; Sergio Spanò (IEEE Access, 2024)

A Novel Digital Equalizer Based on RF Sampling Beyond GHz. - Lorenzo Canese; Gian Carlo Cardarilli; Riccardo La Cesa; Luca Di Nunzio; Rocco Fazzolari; Daniele Giardino; Marco Re; Sergio Spanò (IEEE Access, 2024)

Probability-based mapping approach for an application-aware networks-on-chip architectures. - Deepa Perumal; Aravindhan Alagarsamy; Sundarakannan Mahilmaran; Gian Carlo Cardarilli; Seok-Bum Ko (Nano Commun. Networks, 2024)

High efficiency hardware implementation of a ZP-OTFS modulator for next generation high-mobility wireless systems. - Riccardo La Cesa; Simone Acciarito; Gian Carlo Cardarilli; Luca Di Nunzio; Marco Re; Sergio Spanò; Cristian Valenti (Comput. Electr. Eng., 2025)

Reliable Synchronous and Asynchronous Counter Design in QCA. - Y. S. S. Gowri Sai Saketha; Aravindhan Alagarsamy; Marshal Raj; Gian Carlo Cardarilli; Seok-Bum Ko (J. Circuits Syst. Comput., 2025)

A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. - Cristina Silvano; Daniele Ielmini; Fabrizio Ferrandi; Leandro Fiorin; Serena Curzel; Luca Benini; Francesco Conti 001; Angelo Garofalo; Cristian Zambelli; Enrico Calore; Sebastiano Fabio Schifano; Maurizio Palesi; et al. (ACM Comput. Surv., 2025)