A bibliometric study of literature on digital libraries. - Gian Singh; Rekha Mittal; Moin Ahmad (Electron. Libr., 2007)

Threshold Logic in a Flash. - Ankit Wagle; Gian Singh; Jinghua Yang; Sunil P. Khatri; Sarma B. K. Vrudhula (ICCD, 2019)

CIDAN: Computing in DRAM with Artificial Neurons. - Gian Singh; Ankit Wagle; Sarma B. K. Vrudhula; Sunil P. Khatri (ICCD, 2021)

Tunable Precision Control for Approximate Image Filtering in an In-Memory Architecture with Embedded Neurons. - Ayushi Dube; Ankit Wagle; Gian Singh; Sarma B. K. Vrudhula (ICCAD, 2022)

A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells. - Ankit Wagle; Gian Singh; Sunil P. Khatri; Sarma B. K. Vrudhula (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

PARAG: PIM Architecture for Real-Time Acceleration of GCNs. - Gian Singh; Sanmukh R. Kuppannagari; Sarma B. K. Vrudhula (HiPC, 2023)

A DRAM-based Near-Memory Architecture for Accelerated and Energy-Efficient Execution of Transformers. - Gian Singh; Sarma B. K. Vrudhula (ACM Great Lakes Symposium on VLSI, 2024)

Hardware-Software Co-Design for Path Planning by Drones. - Ayushi Dube; Omkar Patil; Gian Singh; Nakul Gopalan; Sarma B. K. Vrudhula (IROS, 2024)

Energy-Efficient and Low-Latency Computation of Transcendental Functions in a Precision-Tunable PIM Architecture. - Gian Singh; Ayushi Dube; Sarma B. K. Vrudhula (ISVLSI, 2024)

A High Throughput, Energy-Efficient Architecture for Variable Precision Computing in DRAM. - Gian Singh; Ayushi Dube; Sarma B. K. Vrudhula (VLSI-SoC, 2024)

An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency. - Ankit Wagle; Gian Singh; Sunil P. Khatri; Sarma B. K. Vrudhula (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Scalable and Energy-Efficient Processing-in-Memory Architecture for Gen-AI. - Gian Singh; Sarma Vrudhula (IEEE J. Emerg. Sel. Topics Circuits Syst., 2025)