Timing optimization of FPGA placements by logic replication. - Giancarlo Beraudo; John Lillis (DAC, 2003)

An Approach to Placement-Coupled Logic Replication. - Milos Hrkic; John Lillis; Giancarlo Beraudo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)