Investigations on double-diffused MOS transistors under ESD zap conditions. - Gianluca Boselli; Stan Meeuwsen; Ton J. Mouthaan; Fred G. Kuper (Microelectron. Reliab., 2001)

Trends and challenges to ESD and Latch-up designs for nanometer CMOS technologies. - Gianluca Boselli; Charvaka Duvvury (Microelectron. Reliab., 2005)

A MOSFET power supply clamp with feedback enhanced triggering for ESD protection in advanced CMOS technologies. - Jeremy C. Smith; Gianluca Boselli (Microelectron. Reliab., 2005)

Gate oxide failures due to anomalous stress from HBM ESD testers. - Charvaka Duvvury; Robert Steinhoff; Gianluca Boselli; Vijay Reddy; Hans Kunz; Steve Marum; Roger Cline (Microelectron. Reliab., 2006)

Electronic design automation (EDA) solutions for ESD-robust design and verification. - Michael G. Khazhinsky; Shuqing Cao; Harald Gossner; Gianluca Boselli; Melanie Etherton (CICC, 2012)

ESD design challenges in state-of-the-art analog technologies. - Gianluca Boselli (Microelectron. Reliab., 2012)

Improved inductive-system-level IEC ESD performance for automotive applications using mutual ballasted ESD protection technique. - Akram A. Salman; Farzan Farbiz; Ann Concannon; Hal Edwards; Gianluca Boselli (Microelectron. Reliab., 2016)

Physical Insights into the Low Current ESD Failure of LDMOS-SCR and its Implication on Power Scalability. - Nagothu Karmel Kranthi; Boeila Sampath Kumar; Akram A. Salman; Gianluca Boselli; Mayank Shrivastava (IRPS, 2019)

Current Filament Dynamics Under ESD Stress in High Voltage (Bidirectional) SCRs and It's Implications on Power Law Behavior. - Nagothu Karmel Kranthi; Akram A. Salman; Gianluca Boselli; Mayank Shrivastava (IRPS, 2019)

How to Achieve Moving Current Filament in High Voltage LDMOS Devices: Physical Insights & Design Guidelines for Self-Protected Concepts. - Nagothu Karmel Kranthi; Chirag Garg; Boeila Sampath Kumar; Akram A. Salman; Gianluca Boselli; Mayank Shrivastava (IRPS, 2020)

Design Insights to Address Low Current ESD Failure and Power Scalability Issues in High Voltage LDMOS-SCR Devices. - Nagothu Karmel Kranthi; Boeila Sampath Kumar; Akram A. Salman; Gianluca Boselli; Mayank Shrivastava (IRPS, 2020)

Effect of Source & Drain Side Abutting on the Low Current Filamentation in LDMOS-SCR Devices. - M. Monishmurali; Nagothu Karmel Kranthi; Gianluca Boselli; Mayank Shrivastava (IRPS, 2022)

TCAD Investigation of Power-to-Failure Evaluation for Ultrafast Events in BJT-based ESD Protection Cells. - Laura Zunarelli; Susanna Reggiani; Elena Gnani; Raj Sankaralingam; Mariano Dissegna; Gianluca Boselli (IRPS, 2022)

Impact of Thin-oxide Gate on the On-Resistance of HV-PNP Under ESD Stress. - M. Monishmurali; Nagothu Karmel Kranthi; Gianluca Boselli; Mayank Shrivastava (IRPS, 2023)

TCAD study of the Holding-Voltage Modulation in Irradiated SCR-LDMOS for HV ESD Protection. - Laura Zunarelli; Luigi Balestra; Susanna Reggiani; Raj Sankaralingam; Mariano Dissegna; Gianluca Boselli (IRPS, 2023)