A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference. - Gianmarco Ottavi; Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti 001; Luca Benini; Davide Rossi (ISVLSI, 2020)

A transprecision floating-point cluster for efficient near-sensor data analytics. - Fabio Montagna; Stefan Mach; Simone Benatti; Angelo Garofalo; Gianmarco Ottavi; Luca Benini; Davide Rossi; Giuseppe Tagliavini (CoRR, 2020)

End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet? - Gianmarco Ottavi; Geethan Karunaratne; Francesco Conti 001; Irem Boybat; Luca Benini; Davide Rossi (AICAS, 2021)

A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. - Angelo Garofalo; Gianmarco Ottavi; Alfio Di Mauro; Francesco Conti 001; Giuseppe Tagliavini; Luca Benini; Davide Rossi (ESSCIRC, 2021)

A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks. - Angelo Garofalo; Gianmarco Ottavi; Francesco Conti 001; Geethan Karunaratne; Irem Boybat; Luca Benini; Davide Rossi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics. - Fabio Montagna; Stefan Mach; Simone Benatti; Angelo Garofalo; Gianmarco Ottavi; Luca Benini; Davide Rossi; Giuseppe Tagliavini (IEEE Trans. Parallel Distributed Syst., 2022)

Reducing Load-Use Dependency-Induced Performance Penalty in the Open-Source RISC-V CVA6 CPU. - Gianmarco Ottavi; Florian Zaruba; Luca Benini; Davide Rossi (DSD, 2023)

A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Davide Rossi; Gianna Paulin; Angelo Garofalo; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Vincent Huard; Olivier Montfort; Lionel Jure; et al. (ISSCC, 2023)

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Gianna Paulin; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Luca Benini (CoRR, 2023)

Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode. - Gianmarco Ottavi; Angelo Garofalo; Giuseppe Tagliavini; Francesco Conti 001; Alfio Di Mauro; Luca Benini; Davide Rossi (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. - Gianna Paulin; Paul Scheffler; Thomas Benz; Matheus A. Cavalcante; Tim Fischer 001; Manuel Eggimann; Yichao Zhang 003; Nils Wistoff; Luca Bertaccini; Luca Colagrande; Gianmarco Ottavi; Frank K. Gürkaynak; et al. (VLSI Technology and Circuits, 2024)

Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor. - Riccardo Tedeschi; Luca Valente; Gianmarco Ottavi; Enrico Zelioli; Nils Wistoff; Massimiliano Giacometti; Abdul Basit Sajjad; Luca Benini; Davide Rossi (CoRR, 2024)

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Gianna Paulin; Angelo Garofalo; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Luca Benini (IEEE J. Solid State Circuits, 2024)

Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution. - Zexin Fu; Riccardo Tedeschi; Gianmarco Ottavi; Nils Wistoff; César Fuguet; Davide Rossi; Luca Benini (CF, 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (CoRR, 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (IEEE J. Solid State Circuits, 2025)

CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture. - Riccardo Tedeschi; Gianmarco Ottavi; Côme Allart; Nils Wistoff; Zexin Fu; Filippo Grillotti; Fabio De Ambroggi; Elio Guidetti; Jean-Baptiste Rigaud; Olivier Potin; Jean-Roch Coulon; César Fuguet; et al. (CoRR, 2025)