Chipmunk: A Systolically Scalable 0.9 mm2, 3.08 Gop/s/mW @ 1.2 mW Accelerator for Near-Sensor Recurrent Neural Network Inference. - Francesco Conti 001; Lukas Cavigelli; Gianna Paulin; Igor Susmelj; Luca Benini (CoRR, 2017)

Chipmunk: A systolically scalable 0.9 mm2, 3.08Gop/s/mW @ 1.2 mW accelerator for near-sensor recurrent neural network inference. - Francesco Conti 001; Lukas Cavigelli; Gianna Paulin; Igor Susmelj; Luca Benini (CICC, 2018)

RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures. - Gianna Paulin; Renzo Andri; Francesco Conti 001; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2021)

MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores. - Luca Bertaccini; Gianna Paulin; Tim Fischer 001; Stefan Mach; Luca Benini (ARITH, 2022)

Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. - Gianna Paulin; Matheus A. Cavalcante; Paul Scheffler; Luca Bertaccini; Yichao Zhang 003; Frank K. Gürkaynak; Luca Benini (ISVLSI, 2022)

CONVOLVE: Smart and seamless design of smart edge processors. - Manil Dev Gomony; Floran de Putter; Anteneh Gebregiorgis; Gianna Paulin; Linyan Mei; Vikram Jain; Said Hamdioui; Victor Sanchez; Tobias Grosser; Marc Geilen; Marian Verhelst; Frank K. Zenke; et al. (CoRR, 2022)

Vau Da Muntanialas: Energy-Efficient Multi-Die Scalable Acceleration of RNN Inference. - Gianna Paulin; Francesco Conti 001; Lukas Cavigelli; Luca Benini (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

PetaOps/W edge-AI $ mu$ Processors: Myth or reality? - Manil Dev Gomony; Floran de Putter; Anteneh Gebregiorgis; Gianna Paulin; Linyan Mei; Vikram Jain; Said Hamdioui; Victor Sanchez; Tobias Grosser; Marc Geilen; Marian Verhelst; Friedemann Zenke; et al. (DATE, 2023)

ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers. - Gamze Islamoglu; Moritz Scherer 001; Gianna Paulin; Tim Fischer 001; Victor J. B. Jung; Angelo Garofalo; Luca Benini (ISLPED, 2023)

A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Davide Rossi; Gianna Paulin; Angelo Garofalo; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Vincent Huard; Olivier Montfort; Lionel Jure; et al. (ISSCC, 2023)

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Gianna Paulin; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Luca Benini (CoRR, 2023)

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. - Gianna Paulin; Paul Scheffler; Thomas Benz; Matheus A. Cavalcante; Tim Fischer 001; Manuel Eggimann; Yichao Zhang 003; Nils Wistoff; Luca Bertaccini; Luca Colagrande; Gianmarco Ottavi; Frank K. Gürkaynak; et al. (VLSI Technology and Circuits, 2024)

MiniFloats on RISC-V Cores: ISA Extensions With Mixed-Precision Short Dot Products. - Luca Bertaccini; Gianna Paulin; Matheus A. Cavalcante; Tim Fischer 001; Stefan Mach; Luca Benini (IEEE Trans. Emerg. Top. Comput., 2024)

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing. - Francesco Conti 001; Gianna Paulin; Angelo Garofalo; Davide Rossi; Alfio Di Mauro; Georg Rutishauser; Gianmarco Ottavi; Manuel Eggimann; Hayate Okuhara; Luca Benini (IEEE J. Solid State Circuits, 2024)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (CoRR, 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (IEEE J. Solid State Circuits, 2025)